Patents by Inventor Robert Kraft

Robert Kraft has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6399445
    Abstract: A method of fabricating a semiconductor MOS device and the device wherein there is initially provided a semiconductor substrate having a gate insulator layer thereon and intimate therewith. A region of one of a nitride or oxynitride is formed at the surface region of the layer remote from the substrate having sufficient nitride to act as a barrier against the migration of dopant therethrough to the substrate. A doped polysilicon gate or a metal gate is then formed over the region of a nitride or oxynitride. The amount of nitride in the insulator layer intimate and closely adjacent to the substrate is insufficient to materially alter the characteristics of the device being fabricated. The substrate is preferably silicon, the oxide and nitride are preferably those of silicon and the dopant preferably includes boron. The step of forming a region of one of a nitride or oxynitride includes the step of injecting neutral atomic nitrogen into the surface of the gate insulator layer surface remote from the substrate.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: June 4, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Sunil V. Hattangady, Srikanth Krishnan, Robert Kraft
  • Patent number: 6362111
    Abstract: A process for forming a polysilicon line having linewidths below 0.23 &mgr;m. The layer of polysilicon (20) is deposited over a semiconductor body (10). A layer of bottom anti-reflective coating (BARC) (30) is deposited over the polysilicon layer (20). A resist pattern (40) is formed over the BARC layer (30) using conventional lithography (e.g., deep UV lithography). The BARC layer (30) is etched with an etch chemistry of HBr/O2 using the resist pattern (40) until the endpoint is detected. The BARC layer (30) and resist pattern (40) are then overetched using the same etch chemistry having a selectivity of approximately one-to-one between the BARC and resist. The overetch is a timed etch to control the linewidth reduction in the resist/BARC pattern. The minimum dimension of the pattern (50) is reduced to below the practical resolution limit of the lithography tool. Finally, the polysilicon layer (20) is etched using the reduced width pattern (50).
    Type: Grant
    Filed: August 25, 1999
    Date of Patent: March 26, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Reima Laaksonen, Robert Kraft, James B. Friedmann
  • Patent number: 6294913
    Abstract: Monitor signals are acquired in an interleaved manner during a scan with an MRI system. Frequency changes caused by variations in the polarizing magnetic field B0 are measured using the monitor signals, and these measured frequency changes are employed to compensate image data acquired during the scan.
    Type: Grant
    Filed: November 22, 1999
    Date of Patent: September 25, 2001
    Assignee: GE Medical Systems Global Technology Company LLC
    Inventors: Richard Scott Hinks, Robert A. Kraft, Saban Kurucay
  • Patent number: 6261934
    Abstract: Fabrication of metal-on-conductive-diffusion-barrier-on-gate-dielectric structures is done by: etching the metal, by plasma-assisted anisotropic etching, down to and into the barrier metal; and then etching the remainder of the barrier layer by a dry chemical-downstream-etching process, during which the barrier layer is not exposed to ion bombardment. In the case of tungsten over titanium nitride, high selectivity and good profiles are preferably obtained, by: during the tungsten etch, using a combination of low temperature, relatively low bias, and the addition of nitrogen; and during the titanium nitride etch, using a chemical downstream etch instead of the conventional wet etch (in boiling H2SO4). (This allows better control of undercutting, and eliminates wet strip process.
    Type: Grant
    Filed: December 4, 1998
    Date of Patent: July 17, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Kraft, Antonio L. P. Rotondaro
  • Patent number: 6214736
    Abstract: A plasma process is described which produces an undamaged and uncontaminated silicon surface by consuming silicon by continuous oxidation through a surface oxide layer and a simultaneous etch of the exposed silicon oxide surface. The surface silicon dioxide layer thickness is controlled as an equilibrium between oxide growth from oxygen atoms reaching the silicon surface and etching of the oxide surface. The silicon dioxide protects the silicon surface from plasma damage and from contamination.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: April 10, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Antonio L. P. Rotondaro, Reima Tapani Laaksonen, Robert Kraft, Charlotte M. Appel, Rebecca J. Gale, Katherine E. Violette
  • Patent number: 6136654
    Abstract: An embodiment of the instant invention is a method of forming a dielectric layer, the method comprising the steps of: providing a semiconductor substrate (substrate 12), the substrate having a surface; forming an oxygen-containing layer (layer 14) on the semiconductor substrate; and subjecting the oxygen-containing layer to a nitrogen containing plasma (plasma 16) so that the nitrogen is either incorporated into the oxygen-containing layer (see regions 18, 19, and 20) or forms a nitride layer at the surface of the substrate (region 22). Using this embodiment of the instant invention, the dielectric layer can be substantially free of hydrogen. Preferably, the oxygen-containing layer is an SiO.sub.2 layer or it is comprised of oxygen and nitrogen (preferably an oxynitride layer). The plasma is, preferably, a high-density plasma. Preferably, a source of nitrogen is introduced to the plasma to form the nitrogen containing plasma. The source of nitrogen is preferably comprised of a material consisting of: N.sub.
    Type: Grant
    Filed: December 4, 1997
    Date of Patent: October 24, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Kraft, Sunil Hattangady, Douglas T. Grider
  • Patent number: 5796151
    Abstract: In an integrated circuit, gate electrode stack of which is subjected to self-alignment processes, the sheet resistance is lowered by including a tungsten layer 15. The tungsten layer 14 is protected by a sidewall material 21 of SiN.sub.x or SiO.sub.2 after an etching step which did not extend to the substrate 11. During a subsequent etching step in which the stack extends to the substrate 11, the sidewall material 31 acts as a hard mask protecting the upper portion of the stack. After the lower portion of the stack is protected by a re-oxidation layer 41, the entire stack can be processed further without deterioration of the sheet resistance of the tungsten layer 15.
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: August 18, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Wei-Yung Hsu, Dirk N. Anderson, Robert Kraft
  • Patent number: 4894838
    Abstract: A high pressure self-sustained gas laser operating at a high specific energy loading and long pulselength. The laser comprises an endless duct for circulating a laser generating gaseous medium and two discharge electrodes for exciting the molecules of the gaseous medium. Behind the discharge cathode electrode is an electron-beam transmitter for transmitting a beam of preionizing electrons into the gaseous medium to preionize the region near the cathode discharge electrode. The region unpreionized by the electron beam is ionized by drifting electrons from the cathode region and avalanche ionization. The applied discharge voltage never exceeds the glow voltage allowing low discharge flush factors under repetitive operation with flowing laser gas.
    Type: Grant
    Filed: October 19, 1988
    Date of Patent: January 16, 1990
    Inventors: Robert Kraft, Victor H. Hasson