Patents by Inventor Robert L. Borwick
Robert L. Borwick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10416246Abstract: A physics package apparatus for a compact atomic device includes a container having a plurality of slots and an open end, a first vapor cell carrier slidably seated in one of the plurality of slots, a vapor cell coupled to the first vapor cell carrier; and a lid sealably enclosing the open end so that the vapor cell is sealably enclosed in the container.Type: GrantFiled: April 28, 2017Date of Patent: September 17, 2019Assignee: TELEDYNE SCIENTIFIC & IMAGING, LLCInventors: Jeffrey F. DeNatale, Robert L. Borwick, III, Philip A. Stupar, Viktor Tarashansky
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Patent number: 10325707Abstract: A magnetic field coil assembly includes a plurality of stacked dielectric layers, each of the plurality of stacked dielectric layers having a partial-loop conductive trace on a first side of the layer, a via interconnect in communication with the partial-loop conductive trace and extending from the first side of the layer to a side of the layer opposite from the first side, and a vapor cell reception aperture; and a vapor cell axially extending through the plurality of vapor cell reception apertures so that the plurality of partial-loop conductive traces is electrically connected serially to form a continuous coil disposed around the vapor cell that would create a magnetic field upon application of a current.Type: GrantFiled: April 28, 2017Date of Patent: June 18, 2019Assignee: TELEDYNE SCIENTIFIC & IMAGING, LLCInventors: Jeffrey F. DeNatale, Robert L. Borwick, III, Philip A. Stupar, Viktor Tarashansky
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Publication number: 20180315529Abstract: A magnetic field coil assembly includes a plurality of stacked dielectric layers, each of the plurality of stacked dielectric layers having a partial-loop conductive trace on a first side of the layer, a via interconnect in communication with the partial-loop conductive trace and extending from the first side of the layer to a side of the layer opposite from the first side, and a vapor cell reception aperture; and a vapor cell axially extending through the plurality of vapor cell reception apertures so that the plurality of partial-loop conductive traces is electrically connected serially to form a continuous coil disposed around the vapor cell that would create a magnetic field upon application of a current.Type: ApplicationFiled: April 28, 2017Publication date: November 1, 2018Inventors: Jeffrey F. DeNatale, Robert L. Borwick, III, Philip A. Stupar, Viktor Tarashansky
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Publication number: 20180313913Abstract: A physics package apparatus for a compact atomic device includes a container having a plurality of slots and an open end, a first vapor cell carrier slidably seated in one of the plurality of slots, a vapor cell coupled to the first vapor cell carrier; and a lid sealably enclosing the open end so that the vapor cell is sealably enclosed in the container.Type: ApplicationFiled: April 28, 2017Publication date: November 1, 2018Inventors: Jeffrey F. DeNatale, Robert L. Borwick, III, Philip A. Stupar, Viktor Tarashansky
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Patent number: 9607748Abstract: A micro-fabricated electromagnetic device is provided for on-circuit integration. The electromagnetic device includes a core. The core has a plurality of electrically insulating layers positioned alternatingly between a plurality of magnetic layers to collectively form a continuous laminate having alternating magnetic and electrically insulating layers. The electromagnetic device includes a coil embedded in openings of the semiconductor substrate. An insulating material is positioned in the cavity and between the coil and an inner surface of the core. A method of manufacturing the electromagnetic device includes providing a semiconductor substrate having openings formed therein. Windings of a coil are electroplated and embedded in the openings. The insulating material is coated on or around an exposed surface of the coil.Type: GrantFiled: September 3, 2014Date of Patent: March 28, 2017Assignee: Teledyne Scientific & Imaging, LLCInventors: Robert E. Mihailovich, Alex P. Papavasiliou, Vivek Mehrotra, Philip A. Stupar, Robert L. Borwick, III, Rahul Ganguli, Jeffrey F. DeNatale
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Publication number: 20160064470Abstract: A micro-fabricated electromagnetic device is provided for on-circuit integration. The electromagnetic device includes a core. The core has a plurality of electrically insulating layers positioned alternatingly between a plurality of magnetic layers to collectively form a continuous laminate having alternating magnetic and electrically insulating layers. The electromagnetic device includes a coil embedded in openings of the semiconductor substrate. An insulating material is positioned in the cavity and between the coil and an inner surface of the core. A method of manufacturing the electromagnetic device includes providing a semiconductor substrate having openings formed therein. Windings of a coil are electroplated and embedded in the openings. The insulating material is coated on or around an exposed surface of the coil.Type: ApplicationFiled: September 3, 2014Publication date: March 3, 2016Inventors: Robert E. Mihailovich, Alex P. Papavasiliou, Vivek Mehrotra, Philip A. Stupar, Robert L. Borwick, III, Rahul Ganguli, Jeffrey F. DeNatale
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Publication number: 20150185416Abstract: The present disclosure discloses silicon waveguides with embedded active circuitry fabricated from silicon wafers utilizing photolithographic microfabrication techniques to define waveguide structures and embedded circuit recesses for receiving integrated circuitry. The method of fabricating the waveguides utilizes a double masking layer, one layer of which at least partially defines at least one waveguide and the other layer of which at least partially defines the at least one waveguide and at least one embedded circuit recess. The photolithographic microfabrication techniques are sufficiently precise for the required small structural features of high frequency waveguides and the double masking layer allows the method to be completed more efficiently. The basic fabrication method may be extended to provide batch arrays to mass produce silicon waveguide devices.Type: ApplicationFiled: March 13, 2015Publication date: July 2, 2015Inventors: Philip A. Stupar, Robert L. Borwick, III, Robert E. Mihailovich, Jeffrey F. DeNatale
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Patent number: 8995800Abstract: A method of fabricating silicon waveguides with embedded active circuitry from silicon-on-insulator wafers utilizes photolithographic microfabrication techniques to define waveguide structures and embedded circuit recesses for receiving integrated circuitry. The method utilizes a double masking layer, one layer of which at least partially defines at least one waveguide and the other layer of which at least partially defines the at least one waveguide and at least one embedded circuit recess. The photolithographic microfabrication techniques are sufficiently precise for the required small structural features of high frequency waveguides and the double masking layer allows the method to be completed more efficiently. The basic fabrication method may be extended to provide batch arrays to mass produce silicon waveguide devices.Type: GrantFiled: July 6, 2012Date of Patent: March 31, 2015Assignee: Teledyne Scientific & Imaging, LLCInventors: Philip A. Stupar, Robert L. Borwick, III, Robert E. Mihailovich, Jeffrey F. DeNatale
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Patent number: 8937513Abstract: An apparatus includes a chip-scale atomic clock (CSAC) alkali vapor cell seated on a silicon substrate that is suspended in a package by a metalized Parylene strap having Parylene anchors embedded in a silicon frame, the Parylene strap comprising an extended rigidizing structure, and a plurality of electrical pins extending into an interior of the package, the plurality of electrical pins in electrical communication with the CSAC cell through the metalized Parylene strap, where the CSAC cell is mechanically connected to the package and thermally insulated from the package.Type: GrantFiled: May 9, 2013Date of Patent: January 20, 2015Assignee: Teledyne Scientific & Imaging, LLC.Inventors: Jeffrey F. DeNatale, Philip A. Stupar, Yu-Hua Lin, Robert L. Borwick, III, Alexandros P. Papavasiliou
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Patent number: 8826514Abstract: Microfabricated inductors with through-wafer vias and including a first wafer and a second wafer, each wafer having a plurality of metal fillings therein, and a plurality of metal conductors connecting the plurality of metal fillings together to form a spiral. A method for producing an inductor including steps of forming a first plurality of vias in a first substrate, filling the first plurality of vias in the first substrate with a first plurality of metal fillings, forming a first plurality of metal conductors, connecting pairs of the first plurality of metal fillings together using the first plurality of metal conductors to form a spiral, performing the foregoing steps similarly on a second substrate formed with a second plurality of vias filled with a second plurality of metal fillings, and bonding the first substrate with the second substrate.Type: GrantFiled: February 14, 2011Date of Patent: September 9, 2014Assignee: Teledyne Scientific & Imaging, LLCInventors: Alexandros Papavasiliou, Jeffrey F. DeNatale, Philip A. Stupar, Robert L. Borwick, III
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Publication number: 20140205231Abstract: A method of fabricating silicon waveguides with embedded active circuitry from silicon-on-insulator wafers utilizes photolithographic microfabrication techniques to define waveguide structures and embedded circuit recesses for receiving integrated circuitry. The method utilizes a double masking layer, one layer of which at least partially defines at least one waveguide and the other layer of which at least partially defines the at least one waveguide and at least one embedded circuit recess. The photolithographic microfabrication techniques are sufficiently precise for the required small structural features of high frequency waveguides and the double masking layer allows the method to be completed more efficiently. The basic fabrication method may be extended to provide batch arrays to mass produce silicon waveguide devices.Type: ApplicationFiled: July 6, 2012Publication date: July 24, 2014Inventors: PHILIP A. STUPAR, Robert L. Borwick, III, Robert E. Mihailovich, Jeffrey F. DeNatale
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Patent number: 8654332Abstract: A method is disclosed for manufacturing a chip-scale optics module for an optical interrogator. The method includes aligning a polarization axis of a linear polarizer to an angle of 45 degrees from a fast axis of a quarter wave plate to enable circular polarization of a beam, when a beam is introduced to the linear polarizer, coupling the linear polarizer to the quarter wave plate after the aligning to form a circular polarizing filter sheet and then dicing the circular polarizing filter sheet to obtain a plurality of chip-scale circular polarizing filters. Each of the chip-scale circular polarizing filters is diced to have an edge that defines a polarization location index for the linear polarizer. A linear polarizer plate face of one of the chip-scale circular polarizing filters is then positioned so that the linear polarizer plate face is aligned with and parallel to an output face of a laser, whereby the polarization axis of the linear polarizer is not orthogonal to a polarization axis of the laser.Type: GrantFiled: June 22, 2011Date of Patent: February 18, 2014Assignee: Teledyne Scientific & Imaging, LLCInventors: Robert L. Borwick, Jeffrey F DeNatale
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Patent number: 8614610Abstract: A waveguide component encapsulation device may include a housing having first and second surfaces, the housing defining a channel extending through the first and second surfaces, a micromachined waveguide component configured to be positioned in the channel, the waveguide component having first and second ends extending outside the channel and beyond the first and second surfaces of the housing by a finite length, and a pair of spacing members configured to align and stabilize the waveguide component within the channel.Type: GrantFiled: September 7, 2010Date of Patent: December 24, 2013Assignee: Teledyne Scientific & Imaging, LLCInventors: Jonathan Hacker, Chris Hillman, Mark Field, Robert L. Borwick, III
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Publication number: 20130293314Abstract: An apparatus includes a chip-scale atomic clock (CSAC) alkali vapor cell seated on a silicon substrate that is suspended in a package by a metalized Parylene strap having Parylene anchors embedded in a silicon frame, the Parylene strap comprising an extended rigidizing structure, and a plurality of electrical pins extending into an interior of the package, the plurality of electrical pins in electrical communication with the CSAC cell through the metalized Parylene strap, where the CSAC cell is mechanically connected to the package and thermally insulated from the package.Type: ApplicationFiled: May 9, 2013Publication date: November 7, 2013Applicant: Teledyne Scientific & Imaging, LLCInventors: Jeffrey F. DeNatale, Philip A. Stupar, Yu-Hua Lin, Robert L. Borwick, III, Alexandros P. Papavasiliou
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Patent number: 8456249Abstract: A microscale apparatus includes a microscale rigidized Parylene strap having a reinforcement structure extending from a first side of the strap, a first silicon substrate suspended by the microscale rigidized Parylene strap, the microscale rigidized Parylene strap conformally coupled to the first substrate, and a second substrate conformally coupled to the microscale rigidized Parylene strap to suspend the first silicon substrate through the microscale rigidized Parylene strap.Type: GrantFiled: May 11, 2011Date of Patent: June 4, 2013Assignee: Teledyne Scientific & Imaging, LLC.Inventors: Jeffrey F. DeNatale, Philip A. Stupar, Yu-Hua Lin, Robert L. Borwick, Alexandros P. Papavasiliou
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Publication number: 20120327413Abstract: A method is disclosed for manufacturing a chip-scale optics module for an optical interrogator. The method includes aligning a polarization axis of a linear polarizer to an angle of 45 degrees from a fast axis of a quarter wave plate to enable circular polarization of a beam, when a beam is introduced to the linear polarizer, coupling the linear polarizer to the quarter wave plate after the aligning to form a circular polarizing filter sheet and then dicing the circular polarizing filter sheet to obtain a plurality of chip-scale circular polarizing filters. Each of the chip-scale circular polarizing filters is diced to have an edge that defines a polarization location index for the linear polarizer. A linear polarizer plate face of one of the chip-scale circular polarizing filters is then positioned so that the linear polarizer plate face is aligned with and parallel to an output face of a laser, whereby the polarization axis of the linear polarizer is not orthogonal to a polarization axis of the laser.Type: ApplicationFiled: June 22, 2011Publication date: December 27, 2012Inventors: Robert L. Borwick, Jeffrey Denatale
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Patent number: 8319156Abstract: A vapor cell includes an interrogation cell in a substrate, the interrogation cell having an entrance window and an exit window, and a first transparent thin-film heater in thermal communication with the entrance window. The transparent thin-film heater has a first layer in communication with a first pole contact at a proximal end of the heater and a layer coupler contact at a distal end, a second layer in communication with a second pole contact at the proximal end, and the second layer electrically coupled to the layer coupler contact at the distal end. An insulating layer is sandwiched between the first and second layers. The insulating layer has an opening at the distal end to admit the layer coupler contact and to insulate the remainder of the second layer from the first layer.Type: GrantFiled: December 22, 2009Date of Patent: November 27, 2012Inventors: Robert L. Borwick, III, Jeffrey F. DeNatale, Chialun Tsai, Philip A. Stupar, Ya-Chi Chen
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Publication number: 20120286884Abstract: A microscale apparatus includes a microscale rigidized Parylene strap having a reinforcement structure extending from a first side of the strap, a first silicon substrate suspended by the microscale rigidized Parylene strap, the microscale rigidized Parylene strap conformally coupled to the first substrate, and a second substrate conformally coupled to the microscale rigidized Parylene strap to suspend the first silicon substrate through the microscale rigidized Parylene strap.Type: ApplicationFiled: May 11, 2011Publication date: November 15, 2012Inventors: Jeffrey F. DeNatale, Philip A. Stupar, Yu-Hua Lin, Robert L. Borwick, Alexandros P. Papavasiliou
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Patent number: 8258884Abstract: A system is disclosed for charging a compact vapor cell, including placing an alkali-filled capillary into a reservoir cell formed in a substrate, the reservoir cell in vapor communication with an interrogation cell in the substrate and bonding a transparent window to the substrate on a common face of the reservoir cell and the interrogation cell to form a compact vapor cell. Capillary action in the capillary delays migration of alkali in the alkali-filled capillary from the reservoir cell into the interrogation cell during the bonding.Type: GrantFiled: December 22, 2009Date of Patent: September 4, 2012Inventors: Robert L. Borwick, III, Alan L. Sailer, Jeffrey F. DaNatale, Philip A. Stupar, Chialun Tsai
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Patent number: 8187972Abstract: An through-substrate via fabrication method requires forming a through-substrate via hole in a semiconductor substrate, depositing an electrically insulating, continuous and substantially conformal isolation material onto the substrate and interior walls of the via using ALD, depositing a conductive material into the via and over the isolation material using ALD such that it is electrically continuous across the length of the via hole, and depositing a polymer material over the conductive material such that any continuous top-to-bottom openings present in the via holes are filled by the polymer material. The basic fabrication method may be extended to provide vias with multiple conductive layers, such as coaxial and triaxial vias.Type: GrantFiled: January 26, 2011Date of Patent: May 29, 2012Assignee: Teledyne Scientific & Imaging, LLCInventors: Philip A. Stupar, Jeffrey F. DeNatale, Robert L. Borwick, III, Alexandros P. Papavasiliou