Patents by Inventor Robert Mears
Robert Mears has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240127276Abstract: Example methods and apparatus for associating media devices with a demographic composition of a geographic area are disclosed. Disclosed example apparatus are to obtain a plurality of Internet Protocol addresses assigned to a media device associated with a panel member. Disclosed example apparatus are also to determine a most used Internet Protocol address from the plurality of Internet Protocol addresses, determine a geographic location corresponding to the most used Internet Protocol address, associate a geographic area with the media device in response to a determination that the geographic location corresponds to a location of an internet service provider, determine a demographic profile associated with the geographic area, and associate the demographic profile with the media device.Type: ApplicationFiled: October 9, 2023Publication date: April 18, 2024Applicant: The Nielsen Company (US), LLCInventors: Jan Besehanic, Paul Mears, Joseph G. Milavsky, Robert A. Luff, Arun Ramaswamy, David Howell Wright
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Patent number: 9972685Abstract: A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.Type: GrantFiled: December 3, 2015Date of Patent: May 15, 2018Assignee: ATOMERA INCORPORATEDInventors: Robert Mears, Hideki Takeuchi, Erwin Trautmann
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Patent number: 9406753Abstract: A semiconductor device may include an alternating stack of superlattice and bulk semiconductor layers on a substrate, with each superlattice layer including a plurality of stacked group of layers, and each group of layers of the superlattice layer including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattice and bulk semiconductor layers, and a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions.Type: GrantFiled: November 21, 2014Date of Patent: August 2, 2016Assignee: ATOMERA INCORPORATEDInventors: Robert Mears, Hideki Takeuchi, Erwin Trautmann
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Publication number: 20160099317Abstract: A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.Type: ApplicationFiled: December 3, 2015Publication date: April 7, 2016Inventors: ROBERT MEARS, HIDEKI TAKEUCHI, ERWIN TRAUTMANN
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Patent number: 9275996Abstract: A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.Type: GrantFiled: November 21, 2014Date of Patent: March 1, 2016Assignee: MEARS TECHNOLOGIES, INC.Inventors: Robert Mears, Hideki Takeuchi, Erwin Trautmann
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Publication number: 20150144877Abstract: A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.Type: ApplicationFiled: November 21, 2014Publication date: May 28, 2015Inventors: Robert Mears, Hideki Takeuchi, Erwin Trautmann
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Publication number: 20150144878Abstract: A semiconductor device may include an alternating stack of superlattice and bulk semiconductor layers on a substrate, with each superlattice layer including a plurality of stacked group of layers, and each group of layers of the superlattice layer including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattice and bulk semiconductor layers, and a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions.Type: ApplicationFiled: November 21, 2014Publication date: May 28, 2015Inventors: Robert Mears, Hideki Takeuchi, Erwin Trautmann
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Publication number: 20080012004Abstract: A spintronic device may include at least one superlattice and at least one electrical contact coupled thereto, with the at least one superlattice including a plurality of groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and a spintronic dopant. The spintronic dopant may be constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer. In some embodiments, the repeating structure of a superlattice may not be needed.Type: ApplicationFiled: March 16, 2007Publication date: January 17, 2008Inventors: Xiangyang Huang, Samed Halilov, Jean Augustin Yiptong, Ilija Dukovski, Marek Hytha, Robert Mears
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Publication number: 20070238274Abstract: A method is for making a spintronic device and may include forming at least one superlattice and at least one electrical contact coupled thereto, with the at least one superlattice including a plurality of groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and a spintronic dopant. The spintronic dopant may be constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer. In some embodiments, the repeating structure of a superlattice may not be needed.Type: ApplicationFiled: March 16, 2007Publication date: October 11, 2007Applicants: RJ Mears, LLCInventors: Xiangyang HUANG, Samed HALILOV, Jean Chan Sow Fook YIPTONG, Ilija DUKOVSKI, Marek HYTHA, Robert MEARS
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Publication number: 20070194298Abstract: A semiconductor device may include a first monocrystalline layer comprising a first material having a first lattice constant. A second monocrystalline layer may include a second material having a second lattice constant different than the first lattice constant. The device may also include a lattice matching layer between the first and second monocrystalline layers and comprising a superlattice. The superlattice may include a plurality of groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween.Type: ApplicationFiled: February 21, 2007Publication date: August 23, 2007Applicant: RJ Mears, LLCInventors: Ilija Dukovski, Robert Stephenson, Jean Augustin Yiptong, Samed Halilov, Robert Mears, Xiangyang Huang, Marek Hytha
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Publication number: 20070197006Abstract: A method for making a semiconductor device which may include forming a first monocrystalline layer comprising a first material having a first lattice constant, a second monocrystalline layer including a second material having a second lattice constant different than the first lattice constant, and a lattice matching layer between the first and second monocrystalline layers and comprising a superlattice. More particularly, the superlattice may include a plurality of groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. Furthermore, the at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween.Type: ApplicationFiled: February 21, 2007Publication date: August 23, 2007Applicant: RJ Mears, LLCInventors: Ilija Dukovski, Robert Stephenson, Jean Augustin Chan Yiptong, Samed Halilov, Robert Mears, Xiangyang Huang, Marek Hytha
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Publication number: 20070187667Abstract: An electronic device may include a selectively polable superlattice comprising a plurality of stacked groups of layers. Each group of layers of the selectively polable superlattice may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent silicon portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The electronic device may also include at least one electrode for selectively poling the selectively polable superlattice.Type: ApplicationFiled: December 21, 2006Publication date: August 16, 2007Applicant: RJ Mears, LLCInventors: Samed Halilov, Xiangyang Huang, Ilija Dukovski, Jean Augustin Chan Yiptong, Robert Mears, Marek Hytha, Robert Stephenson
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Publication number: 20070166928Abstract: A method for making an electronic device may include forming a selectively polable superlattice comprising a plurality of stacked groups of layers. Each group of layers of the selectively polable superlattice may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent silicon portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include coupling at least one electrode to the selectively polable superlattice for selective poling thereof.Type: ApplicationFiled: December 21, 2006Publication date: July 19, 2007Applicant: RJ Mears, LLCInventors: Samed Halilov, Xiangyang Huang, Ilija Dukovski, Jean Augustin Yiptong, Robert Mears, Marek Hytha, Robert Stephenson
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Publication number: 20070161138Abstract: A method for making an electronic device may include forming a poled superlattice comprising a plurality of stacked groups of layers and having a net electrical dipole moment. Each group of layers of the poled superlattice may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include coupling at least one electrode to the poled superlattice.Type: ApplicationFiled: December 21, 2006Publication date: July 12, 2007Applicant: RJ Mears, LLCInventors: Samed Halilov, Xiangyang Huang, Ilija Dukovski, Jean Augustin Yiptong, Robert Mears, Marek Hytha, Robert Stephenson
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Publication number: 20070158640Abstract: An electronic device may include a poled superlattice comprising a plurality of stacked groups of layers and having a net electrical dipole moment. Each group of layers of the poled superlattice may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The electronic device may further include at least one electrode coupled to the poled superlattice.Type: ApplicationFiled: December 21, 2006Publication date: July 12, 2007Applicant: RJ Mears, LLCInventors: Samed Halilov, Xiangyang Huang, Ilija Dukovski, Jean Augustin Yiptong, Robert Mears, Marek Hytha, Robert Stephenson
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Publication number: 20070020860Abstract: A method for making a semiconductor device may include forming a superlattice layer including a plurality of stacked groups of layers, and forming a stress layer above the strained superlattice layer to induce a strain therein. Each group of layers of the superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.Type: ApplicationFiled: July 13, 2006Publication date: January 25, 2007Applicant: RJ Mears, LLCInventors: Robert Mears, Scott Kreps
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Publication number: 20070020833Abstract: A method for making a semiconductor device may include forming at least one metal oxide semiconductor field-effect transistor (MOSFET) on a semiconductor substrate. The MOSFET may include spaced-apart source and drain regions, a channel between the source and drain regions, and a gate overlying the channel defining an interface therewith. The gate may include a gate dielectric overlying the channel and a gate electrode overlying the gate dielectric. The channel may include a plurality of stacked base semiconductor monolayers, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor monolayers. The at least one non-semiconductor monolayer may be positioned at depth of about 4-100 monolayers relative to the interface between the channel and the gate dielectric.Type: ApplicationFiled: July 13, 2006Publication date: January 25, 2007Applicant: RJ Mears, LLCInventors: Robert Mears, Marek Hytha, Scott Kreps
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Publication number: 20070012912Abstract: A semiconductor device may include a strained superlattice layer including a plurality of stacked groups of layers, and a stress layer above the strained superlattice layer. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.Type: ApplicationFiled: July 13, 2006Publication date: January 18, 2007Applicant: RJ Mears, LLCInventors: Robert Mears, Scott Kreps
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Publication number: 20070012910Abstract: A semiconductor device may include a semiconductor substrate, and at least one metal oxide semiconductor field-effect transistor (MOSFET) thereon. The MOSFET may include spaced-apart source and drain regions, a channel between the source and drain regions, and a gate overlying the channel defining an interface therewith. The gate may include a gate dielectric overlying the channel and a gate electrode overlying the gate dielectric. The channel may include a plurality of stacked base semiconductor monolayers, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor monolayers. The at least one non-semiconductor monolayer may be positioned at depth of about 4-100 monolayers relative to the interface between the channel and the gate dielectric.Type: ApplicationFiled: July 13, 2006Publication date: January 18, 2007Applicant: RJ Mears, LLCInventors: Robert Mears, Marek Hytha, Scott Kreps
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Publication number: 20070012909Abstract: A semiconductor device may include at least one pair of spaced apart stress regions, and a strained superlattice layer between the at least one pair of spaced apart stress regions and including a plurality of stacked groups of layers. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.Type: ApplicationFiled: July 13, 2006Publication date: January 18, 2007Applicant: RJ Mears, LLCInventors: Robert Mears, Scott Kreps