Patents by Inventor Robert Reid

Robert Reid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180352791
    Abstract: Various embodiments of an aquarium and its method of use are disclosed. In some embodiments, the aquarium includes a first container for holding water and fish, plants, and/or other aquatic organism, a second container for collecting dirty water, and a passageway arranged to flush water from the first container to the second container. The passageway is in fluid communication with an outlet of the first container. The second container is arranged to receive the outlet such that fluid flows from the passageway, through the outlet, and into the second container. The outlet may be selectively opened by a user via a valve. Opening the valve causes gravity to flush water and debris from the first container, through the passageway, through the valve and into the second container, where the dirty water can be stored or discarded by disconnecting the second container from the aquarium ad dumping the dirty water.
    Type: Application
    Filed: June 9, 2017
    Publication date: December 13, 2018
    Inventor: Robert Reid
  • Publication number: 20180348461
    Abstract: A channel equalization enclosure equalizes the length of cable variance with customers' equipment in a data center. The channel equalization modules serve as a connection point between cable from a financial institution and patch cords connected to customer equipment. The channel equalization enclosure includes a housing and a plurality of channel equalization modules mounted in the housing. Each channel equalization module has a spool of bulk fiber for accommodating a specified fiber length to equalize a communication channel in the data center.
    Type: Application
    Filed: May 25, 2018
    Publication date: December 6, 2018
    Applicant: Panduit Corp.
    Inventors: Bon B. Sledzinski, Robert A. Reid, Joseph E. Sanders
  • Publication number: 20180263224
    Abstract: Filtering device (20) to draw water from an aquarium and the like and make water circulate inside, including a container (30) comprising a first housing portion (32) having a first inlet (174) and a second inlet (176) for the entry of water taken from the aquarium into the first housing portion (32) which is able to contain at least one filter for filtering water, further including a flow control device (50) having an entry (60) for taking water from the aquarium and it has two operating positions, a first operating position or filtering position wherein the entry (60) is in communication with the first inlet (174), so that water taken from the aquarium is put into the first housing portion (32), passes through the first inlet (174), is filtered and then is put back into the aquarium, and a second operating position or cleaning position or backwash position, wherein the entry (60) is in communication with the second inlet (176), water taken from the aquarium enters into the first housing portion (32) through
    Type: Application
    Filed: May 18, 2015
    Publication date: September 20, 2018
    Applicant: Rolf C. Hagen Inc.
    Inventors: Valerio Bresolin, Robert Reid
  • Patent number: 10069065
    Abstract: Graphene Hall sensors, magnetic sensor systems and methods for sensing a magnetic field using an adjustable gate voltage to adapt the Hall sensor magnetic field sensitivity according to a control input for environmental or process compensation and/or real-time adaptation for balancing power consumption and minimum detectable field performance. The graphene Hall sensor gate voltage can be modulated and the sensor output signal can be demodulated to combat flicker or other low frequency noise. Also, graphene Hall sensors can be provided with capacitive coupled contacts for reliable low impedance AC coupling to instrumentation amplifiers or other circuits using integral capacitance.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: September 4, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Arup Polley, Archana Venugopal, Robert Reid Doering, Luigi Colombo
  • Patent number: 10060826
    Abstract: Embodiments of the present invention generally relate to the field of optical fiber splicing, and more specifically to apparatuses and methods directed to mechanical splice termination and evaluation of resulting splice joints. In an embodiment, the present invention is an apparatus for evaluating the integrity of a mechanical splice joint comprising a light source, a circulator, a photo detector, and an analysis circuit, wherein the apparatus connects to a test connector and evaluates signals representative of light pulses passing through at least a portion of the test connector.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: August 28, 2018
    Assignee: Panduit Corp.
    Inventors: Brett Lane, Robert A. Reid, Joseph M. Nash
  • Publication number: 20180240886
    Abstract: A microelectronic device includes an electrical conductor which includes a graphene heterolayer. The graphene heterolayer includes a plurality of alternating layers of graphene and barrier material. Each layer of the graphene has one to two atomic layers of graphene. Each layer of the barrier material has one to three layers of hexagonal boron nitride, cubic boron nitride, and/or aluminum nitride. The layers of graphene and the layers of barrier material may be continuous, or may be disposed in nanoparticles of a nanoparticle film.
    Type: Application
    Filed: February 21, 2017
    Publication date: August 23, 2018
    Applicant: Texas Instruments Incorporated
    Inventors: Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo, Robert Reid Doering
  • Publication number: 20180151487
    Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.
    Type: Application
    Filed: November 26, 2016
    Publication date: May 31, 2018
    Applicant: Texas Instruments Incorporated
    Inventors: Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo, Robert Reid Doering
  • Publication number: 20180153055
    Abstract: Substrate-free mechanical structural systems comprised of interconnected subsystems of electronic and/or electromechanical components.
    Type: Application
    Filed: December 27, 2017
    Publication date: May 31, 2018
    Inventors: Ian Hovey, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille
  • Publication number: 20180151463
    Abstract: An integrated circuit has a thermal routing structure above a top interconnect level. The top interconnect level includes interconnects connected to lower interconnect levels, and does not include bond pads, probe pads, input/output pads, or a redistribution layer to bump bond pads. The thermal routing structure extends over a portion, but not all, of a plane of the integrated circuit containing the top interconnect level. The thermal routing structure includes a layer of nanoparticles in which adjacent nanoparticles are attached to each other. The layer of nanoparticles is free of an organic binder material. The thermal routing structure has a thermal conductivity higher than the metal in the top interconnect level. The layer of nanoparticles is formed by an additive process.
    Type: Application
    Filed: November 26, 2016
    Publication date: May 31, 2018
    Applicant: Texas Instruments Incorporated
    Inventors: Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo, Robert Reid Doering
  • Publication number: 20180151470
    Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region has a plurality of interconnect levels. The integrated circuit includes a thermal routing structure in the interconnect region. The thermal routing structure extends over a portion, but not all, of the integrated circuit in the interconnect region. The thermal routing structure includes a cohered nanoparticle film in which adjacent nanoparticles cohere to each other. The thermal routing structure has a thermal conductivity higher than dielectric material touching the thermal routing structure. The cohered nanoparticle film is formed by a method which includes an additive process.
    Type: Application
    Filed: November 26, 2016
    Publication date: May 31, 2018
    Applicant: Texas Instruments Incorporated
    Inventors: Benjamin Stassen Cook, Archana Venugopal, Luigi Colombo, Robert Reid Doering
  • Publication number: 20180151467
    Abstract: A packaged electronic device includes an integrated circuit and an electrically non-conductive encapsulation material in contact with the integrated circuit. A thermal conduit extends from an exterior of the package, through the encapsulation material, to the integrated circuit. The thermal conduit has a thermal conductivity higher than the encapsulation material contacting the thermal conduit. The thermal conduit includes a cohered nanoparticle film. The cohered nanoparticle film is formed by a method which includes an additive process.
    Type: Application
    Filed: November 26, 2016
    Publication date: May 31, 2018
    Applicant: Texas Instruments Incorporated
    Inventors: Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo, Robert Reid Doering
  • Publication number: 20180151464
    Abstract: An integrated circuit has a substrate which includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.
    Type: Application
    Filed: November 26, 2016
    Publication date: May 31, 2018
    Applicant: Texas Instruments Incorporated
    Inventors: Benjamin Stassen Cook, Archana Venugopal, Luigi Colombo, Robert Reid Doering
  • Publication number: 20180151471
    Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.
    Type: Application
    Filed: November 26, 2016
    Publication date: May 31, 2018
    Applicant: Texas Instruments Incorporated
    Inventors: Benjamin Stassen Cook, Archana Venugopal, Luigi Colombo, Robert Reid Doering
  • Publication number: 20180124007
    Abstract: Examples described herein include receiving text of an email, determining a header of an email message in the email, and determining a body of the email message. Examples also include modifying the text of the email to indicate a beginning boundary and an ending boundary of the header, modifying the text of the email to indicate a beginning boundary and an ending boundary of the body, generating a hash of the header, generating a hash of the body, and tracing the email based on the hash of the header.
    Type: Application
    Filed: October 28, 2016
    Publication date: May 3, 2018
    Inventors: Krzysztof Ploch, Andrew Robert Reid, Dermot Hardy
  • Publication number: 20180123217
    Abstract: Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems.
    Type: Application
    Filed: January 3, 2018
    Publication date: May 3, 2018
    Inventors: Jean-Marc Rollin, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille, J. Marcus Oliver, Tim Smith
  • Publication number: 20180114157
    Abstract: Some examples include a machine-readable storage medium with instructions executable by a processing resource of a device to process a file according to a pre-defined workflow. The machine-readable storage medium comprises instructions to receive a message to process the file at a workflow queue, to forward the file, by a policy workflow worker, to a first workflow process worker that corresponds to the file, and to perform, at the first workflow process worker, a first workflow process on the message. The machine-readable storage medium further comprises instructions to return, by the first workflow process worker, the processed message to the workflow queue, wherein the processed message includes the file and a first result, to evaluate, by the policy workflow worker, the processed message against the pre-defined workflow and, based on the evaluation, to forward the processed message, by the policy workflow worker, to a second workflow process worker or an output queue.
    Type: Application
    Filed: October 20, 2016
    Publication date: April 26, 2018
    Inventors: Michael McAlynn, Andrew Robert Reid, Krzysztof Ploch
  • Patent number: 9888600
    Abstract: Substrate-free mechanical structural systems comprised of interconnected subsystems of electronic and/or electromechanical components are provided.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: February 6, 2018
    Assignee: NUVOTRONICS, INC
    Inventors: Ian Hovey, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille
  • Patent number: 9868763
    Abstract: The present invention provides novel compounds of the Formula (I), pharmaceutical compositions comprising such compounds and methods for using such compounds as tools for biological studies or as agents or drugs for therapies such as metabolic syndrome, obesity, type II diabetes, fibrosis and cardiovascular diseases, whether they are used alone or in combination with other treatment modalities.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: January 16, 2018
    Assignee: The University of Queensland
    Inventors: David Fairlie, Ligong Liu, Mei-Kwan Yau, Jacky Yung Suen, Robert Reid, Rink-Jan Lohman, Abishek Venkatasubramanian Iyer, Junxian Lim, Lindsay Charles Brown
  • Publication number: 20180003912
    Abstract: The present invention provides modular trays having cutout features that are configured to engage with a mounting feature of one or more removable rails. The removable rails may be removeably secured to a tray body in a plurality of positions to allow a user to install or uninstall rails to support different sized fiber optic modules. For example, a tray may support a twenty-four optical fiber module, two twelve optical fiber modules, or three eight optical fiber modules. Fiber optic enclosures housing the trays can be affixed to the outside of a fiber optic enclosure and allow for easy stacking and unstacking.
    Type: Application
    Filed: June 21, 2017
    Publication date: January 4, 2018
    Applicant: Panduit Corp.
    Inventors: Thomas M. Sedor, Jerry A. Wiltjer, Robert A. Reid, Joseph E. Sanders, Joel W. Kwasny, Bon B. Sledzinski
  • Patent number: 9845703
    Abstract: A turbine component surface treatment process includes passing a UV-curable maskant through one or more fluid flow passages, wherein at least a portion of the UV-curable maskant exits the one or more fluid flow passages at an exterior surface of the turbine component, applying a UV light to the exterior surface of the turbine component, wherein the UV light cures at least a portion of the UV-curable maskant exiting the one or more fluid flow passages, and, treating the exterior surface with a treatment material, wherein the portion of the UV-curable maskant cured by the UV light substantially blocks the treatment material from entering the one or more fluid flow passages.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: December 19, 2017
    Assignee: General Electric Company
    Inventors: James Carroll Baummer, Thomas Robert Reid