Patents by Inventor Robert Reid

Robert Reid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10553511
    Abstract: Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: February 4, 2020
    Assignee: CUBIC CORPORATION
    Inventor: J. Robert Reid
  • Publication number: 20200022277
    Abstract: Substrate-free mechanical structural systems comprised of interconnected subsystems of electronic and/or electromechanical components.
    Type: Application
    Filed: March 28, 2019
    Publication date: January 16, 2020
    Inventors: Ian Hovey, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille
  • Patent number: 10528904
    Abstract: Some examples include a machine-readable storage medium with instructions executable by a processing resource of a device to process a file according to a pre-defined workflow. The machine-readable storage medium comprises instructions to receive a message to process the file at a workflow queue, to forward the file, by a policy workflow worker, to a first workflow process worker that corresponds to the file, and to perform, at the first workflow process worker, a first workflow process on the message. The machine-readable storage medium further comprises instructions to return, by the first workflow process worker, the processed message to the workflow queue, wherein the processed message includes the file and a first result, to evaluate, by the policy workflow worker, the processed message against the pre-defined workflow and, based on the evaluation, to forward the processed message, by the policy workflow worker, to a second workflow process worker or an output queue.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: January 7, 2020
    Assignee: MICRO FOCUS LLC
    Inventors: Michael McAlynn, Andrew Robert Reid, Krzysztof Ploch
  • Patent number: 10524456
    Abstract: Filtering device (20) to draw water from an aquarium and the like and make water circulate inside, including a container (30) comprising a first housing portion (32) having a first inlet (174) and a second inlet (176) for the entry of water taken from the aquarium into the first housing portion (32) which is able to contain at least one filter for filtering water, further including a flow control device (50) having an entry (60) for taking water from the aquarium and it has two operating positions, a first operating position or filtering position wherein the entry (60) is in communication with the first inlet (174), so that water taken from the aquarium is put into the first housing portion (32), passes through the first inlet (174), is filtered and then is put back into the aquarium, and a second operating position or cleaning position or backwash position, wherein the entry (60) is in communication with the second inlet (176), water taken from the aquarium enters into the first housing portion (32) through
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: January 7, 2020
    Assignee: Rolf C. Hagen Inc.
    Inventors: Valerio Bresolin, Robert Reid
  • Patent number: 10529641
    Abstract: An integrated circuit has a thermal routing structure above a top interconnect level. The top interconnect level includes interconnects connected to lower interconnect levels, and does not include bond pads, probe pads, input/output pads, or a redistribution layer to bump bond pads. The thermal routing structure extends over a portion, but not all, of a plane of the integrated circuit containing the top interconnect level. The thermal routing structure includes a layer of nanoparticles in which adjacent nanoparticles are attached to each other. The layer of nanoparticles is free of an organic binder material. The thermal routing structure has a thermal conductivity higher than the metal in the top interconnect level. The layer of nanoparticles is formed by an additive process.
    Type: Grant
    Filed: November 26, 2016
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo, Robert Reid Doering
  • Publication number: 20190393580
    Abstract: Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems.
    Type: Application
    Filed: January 25, 2019
    Publication date: December 26, 2019
    Inventors: Jean-Marc Rollin, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille, J. Marcus Oliver, Tim Smith
  • Patent number: 10511563
    Abstract: Examples described herein include receiving text of an email, determining a header of an email message in the email, and determining a body of the email message. Examples also include modifying the text of the email to indicate a beginning boundary and an ending boundary of the header, modifying the text of the email to indicate a beginning boundary and an ending boundary of the body, generating a hash of the header, generating a hash of the body, and tracing the email based on the hash of the header.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: December 17, 2019
    Assignee: MICRO FOCUS LLC
    Inventors: Krzysztof Ploch, Andrew Robert Reid, Dermot Hardy
  • Publication number: 20190287869
    Abstract: Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.
    Type: Application
    Filed: June 6, 2019
    Publication date: September 19, 2019
    Inventor: J. Robert Reid
  • Publication number: 20190229051
    Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.
    Type: Application
    Filed: April 2, 2019
    Publication date: July 25, 2019
    Inventors: Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo, Robert Reid Doering
  • Patent number: 10361471
    Abstract: Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: July 23, 2019
    Assignee: NUVOTRONICS, INC
    Inventors: Jean-Marc Rollin, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille, J. Marcus Oliver, Tim Smith
  • Patent number: 10319654
    Abstract: Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: June 11, 2019
    Assignee: CUBIC CORPORATION
    Inventor: J. Robert Reid
  • Publication number: 20190172764
    Abstract: Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.
    Type: Application
    Filed: December 1, 2017
    Publication date: June 6, 2019
    Inventor: J. Robert Reid
  • Publication number: 20190154936
    Abstract: The present invention provides modular trays having cutout features that are configured to engage with a mounting feature of one or more removable rails. The removable rails may be removably secured to a tray body in a plurality of positions to allow a user to install or uninstall rails to support different sized fiber optic modules. For example, a tray may support a twenty-four optical fiber module, two twelve optical fiber modules, or three eight optical fiber modules. Fiber optic enclosures housing the trays can be affixed to the outside of a fiber optic enclosure and allow for easy stacking and unstacking.
    Type: Application
    Filed: January 25, 2019
    Publication date: May 23, 2019
    Applicant: Panduit Corp.
    Inventors: Thomas M. Sedor, Jerry A. Wiltjer, Robert A. Reid, Joseph E. Sanders, Joel D. Kwasny, Bon B. Sledzinski
  • Publication number: 20190138972
    Abstract: A system for gathering and displaying data related to a wearer's performance and satisfaction in performing a job includes a wearable device to be worn by the wearer while performing the job. The wearable device includes sensors and is configured to collect and store data elements with values pertaining to one or more conditions associated with the ambient environment and/or the wearer. The wearable device also includes input and output devices to collect feedback data element regarding the wearer's job satisfaction. A server stores and analyzes the data elements to determine a job satisfaction score for the wearer and a correlation score that indicates a correlation between the job satisfaction values and one or more data elements pertaining to the ambient environment and/or the wearer. A reporting interface reports the job satisfaction and the correlation scores. A control interface allows an administrator to control settings related to operation of the system.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 9, 2019
    Inventor: John Robert Reid
  • Patent number: 10256188
    Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.
    Type: Grant
    Filed: November 26, 2016
    Date of Patent: April 9, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo, Robert Reid Doering
  • Patent number: 10257951
    Abstract: Substrate-free mechanical structural systems comprised of interconnected subsystems of electronic and/or electromechanical components.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: April 9, 2019
    Assignee: NUVOTRONICS, INC
    Inventors: Ian Hovey, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille
  • Patent number: 10215944
    Abstract: The present invention provides modular trays having cutout features that are configured to engage with a mounting feature of one or more removable rails. The removable rails may be removeably secured to a tray body in a plurality of positions to allow a user to install or uninstall rails to support different sized fiber optic modules. For example, a tray may support a twenty-four optical fiber module, two twelve optical fiber modules, or three eight optical fiber modules. Fiber optic enclosures housing the trays can be affixed to the outside of a fiber optic enclosure and allow for easy stacking and unstacking.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: February 26, 2019
    Assignee: Panduit Corp.
    Inventors: Thomas M. Sedor, Jerry A. Wiltjer, Robert A. Reid, Joseph E. Sanders, Joel W. Kwasny, Bon B. Sledzinski
  • Patent number: 10193203
    Abstract: Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: January 29, 2019
    Assignee: NUVOTRONICS, INC
    Inventors: Jean-Marc Rollin, J. Robert Reid, David Sherrer, Will Stacy, Ken Vanhille, J. Marcus Oliver, Tim Smith
  • Patent number: 10181521
    Abstract: A microelectronic device includes an electrical conductor which includes a graphene heterolayer. The graphene heterolayer includes a plurality of alternating layers of graphene and barrier material. Each layer of the graphene has one to two atomic layers of graphene. Each layer of the barrier material has one to three layers of hexagonal boron nitride, cubic boron nitride, and/or aluminum nitride. The layers of graphene and the layers of barrier material may be continuous, or may be disposed in nanoparticles of a nanoparticle film.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: January 15, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo, Robert Reid Doering
  • Patent number: D849590
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: May 28, 2019
    Inventors: Robert Reid Peterson, Andrew Kent Peterson