Patents by Inventor Robert S. Chau
Robert S. Chau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10692839Abstract: GaN-On-Silicon (GOS) structures and techniques for accommodating and/or controlling stress/strain incurred during III-N growth on a large diameter silicon substrate. A back-side of a silicon substrate may be processed to adapt substrates of standardized diameters and thicknesses to GOS applications. Bowing and/or warping during high temperature epitaxial growth processes may be mitigated by pre-processing silicon substrate so as to pre-stress the substrate in a manner than counterbalances stress induced by the III-N material and/or improve a substrate's ability to absorb stress. III-N devices fabricated on an engineered GOS substrate may be integrated together with silicon MOS devices fabricated on a separate substrate. Structures employed to improve substrate resilience and/or counterbalance the substrate stress induced by the III-N material may be further employed for interconnecting the III-N and silicon MOS devices of a 3D IC.Type: GrantFiled: June 26, 2015Date of Patent: June 23, 2020Assignee: Intel CorporationInventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Peter G. Tolchinsky, Robert S. Chau
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Patent number: 10665708Abstract: Semiconductor devices including an elevated or raised doped crystalline structure extending from a device layer are described. In embodiments, III-N transistors include raised crystalline n+ doped source/drain structures on either side of a gate stack. In embodiments, an amorphous material is employed to limit growth of polycrystalline source/drain material, allowing a high quality source/drain doped crystal to grow from an undamaged region and laterally expand to form a low resistance interface with a two-degree electron gas (2DEG) formed within the device layer. In some embodiments, regions of damaged GaN that may spawn competitive polycrystalline overgrowths are covered with the amorphous material prior to commencing raised source/drain growth.Type: GrantFiled: January 8, 2019Date of Patent: May 26, 2020Assignee: Intel CorporationInventors: Marko Radosavljevic, Sansaptak Dasgupta, Sanaz K. Gardner, Seung Hoon Sung, Han Wui Then, Robert S. Chau
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Patent number: 10580973Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF).Type: GrantFiled: December 10, 2018Date of Patent: March 3, 2020Assignee: INTEL CORPORATIONInventors: Brian S. Doyle, Kaan Oguz, Charles C. Kuo, Mark L. Doczy, Satyarth Suri, David L. Kencke, Robert S. Chau, Roksana Golizadeh Mojarad
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Patent number: 10580895Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.Type: GrantFiled: July 19, 2018Date of Patent: March 3, 2020Assignee: Intel CorporationInventors: Han Wui Then, Robert S. Chau, Sansaptak Dasgupta, Marko Radosavljevic, Benjamin Chu-Kung, Seung Hoon Sung, Sanaz Gardner, Ravi Pillarisetty
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Patent number: 10573647Abstract: CMOS circuits may formed using p-channel gallium nitride transistors and n-channel gallium nitride transistors, wherein both the p-channel gallium nitride transistors and the n-channel gallium nitride transistors are formed on a single layered structure comprising a polarization layer deposited on a first gallium nitride layer and a second gallium nitride layer deposited on the polarization layer. Having both n-channel gallium nitride transistors and p-channel gallium nitride transistors s on the same layer structure may enable “all gallium nitride transistor” implementations of circuits including logic, digital, and analog circuitries spanning low supply voltages to high supply voltages.Type: GrantFiled: November 18, 2014Date of Patent: February 25, 2020Assignee: Intel CorporationInventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Robert S. Chau
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Patent number: 10573717Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.Type: GrantFiled: November 21, 2018Date of Patent: February 25, 2020Assignee: Intel CorporationInventors: Niti Goel, Gilbert Dewey, Niloy Mukherjee, Matthew V. Metz, Marko Radosavljevic, Benjamin Chu-Kung, Jack T. Kavalieros, Robert S. Chau
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Publication number: 20200051724Abstract: An embodiment includes an apparatus comprising: a substrate; a magnetic tunnel junction (MTJ), on the substrate, comprising a fixed layer, a free layer, and a dielectric layer between the fixed and free layers; and a first synthetic anti-ferromagnetic (SAF) layer, a second SAF layer, and an intermediate layer, which includes a non-magnetic metal, between the first and second SAF layers; wherein the first SAF layer includes a Heusler alloy. Other embodiments are described herein.Type: ApplicationFiled: June 26, 2015Publication date: February 13, 2020Inventors: Brian S. Doyle, Kaan Oguz, Kevin P. O'Brien, David L. Kencke, Charles C. Kuo, Mark L. Doczy, Satyarth Suri, Robert S. Chau
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Publication number: 20200043536Abstract: An embodiment includes an apparatus comprising: a substrate; a perpendicular magnetic tunnel junction (pMTJ), on the substrate, comprising a first fixed layer, a second fixed layer, and a free layer between the first and second fixed layers; a first dielectric layer between the first fixed layer and the free layer; and a second layer between the second fixed layer and the free layer. Other embodiments are described herein.Type: ApplicationFiled: June 26, 2015Publication date: February 6, 2020Inventors: Charles C. Kuo, Justin S. Brockman, Juan G. Alzate Vinasco, Kaan Oguz, Kevin P. O'Brien, Brian S. Doyle, Mark L. Doczy, Satyarth Suri, Robert S. Chau
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Patent number: 10522739Abstract: An embodiment includes an apparatus comprising: a substrate; and a perpendicular magnetic tunnel junction (pMTJ) comprising a fixed layer and first and second free layers; wherein (a) the first free layer includes Cobalt (Co), Iron (Fe), and Boron (B), and (b) the second free layer is epitaxial and includes Manganese (Mn) and Gallium (Ga). Other embodiments are described herein.Type: GrantFiled: June 26, 2015Date of Patent: December 31, 2019Assignee: Intel CorporationInventors: Kaan Oguz, Kevin P. O'Brien, Brian S. Doyle, David L. Kencke, Charles C. Kuo, Robert S. Chau
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Patent number: 10516109Abstract: Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.Type: GrantFiled: December 24, 2014Date of Patent: December 24, 2019Assignee: Intel CorporationInventors: Niloy Mukherjee, Ravi Pillarisetty, Prashant Majhi, Uday Shah, Ryan E Arch, Markus Kuhn, Justin S. Brockman, Huiying Liu, Elijah V Karpov, Kaan Oguz, Brian S. Doyle, Robert S. Chau
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Publication number: 20190371940Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.Type: ApplicationFiled: July 30, 2019Publication date: December 5, 2019Applicant: Intel CorporationInventors: Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros, Amlan Majumdar, Matthew V. Metz, Marko Radosavljevic
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Publication number: 20190348604Abstract: Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.Type: ApplicationFiled: May 17, 2019Publication date: November 14, 2019Applicant: INTEL CORPORATIONInventors: NILOY MUKHERJEE, RAVI PILLARISETTY, PRASHANT MAJHI, UDAY SHAH, RYAN E ARCH, MARKUS KUHN, JUSTIN S. BROCKMAN, HUIYING LIU, ELIJAH V KARPOV, KAAN OGUZ, BRIAN S. DOYLE, ROBERT S. CHAU
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Patent number: 10475888Abstract: An insulating layer is conformally deposited on a plurality of mesa structures in a trench on a substrate. The insulating layer fills a space outside the mesa structures. A nucleation layer is deposited on the mesa structures. A III-V material layer is deposited on the nucleation layer. The III-V material layer is laterally grown over the insulating layer.Type: GrantFiled: April 20, 2017Date of Patent: November 12, 2019Assignee: Intel CorporationInventors: Sansaptak Dasgupta, Han Wui Then, Seung Hoon Sung, Sanaz K. Gardner, Marko Radosavljevic, Benjamin Chu-Kung, Robert S. Chau
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Patent number: 10475706Abstract: Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystaline defects in the fins due to lattice mismatch in the layer interfaces.Type: GrantFiled: February 10, 2017Date of Patent: November 12, 2019Assignee: Intel CorporationInventors: Niti Goel, Benjamin Chu-Kung, Sansaptak Dasgupta, Niloy Mukherjee, Matthew V. Metz, Van H. Le, Jack T. Kavalieros, Robert S. Chau, Ravi Pillarisetty
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Patent number: 10453679Abstract: Methods and devices integrating circuitry including both III-N (e.g., GaN) transistors and Si-based (e.g., Si or SiGe) transistors. In some monolithic wafer-level integration embodiments, a silicon-on-insulator (SOI) substrate is employed as an epitaxial platform providing a first silicon surface advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N transistors (e.g., III-N HFETs) are formed, and a second silicon surface advantageous for seeding an epitaxial raised silicon upon which Si-based transistors (e.g., Si FETs) are formed. In some heterogeneous wafer-level integration embodiments, an SOI substrate is employed for a layer transfer of silicon suitable for fabricating the Si-based transistors onto another substrate upon which III-N transistors have been formed. In some such embodiments, the silicon layer transfer is stacked upon a planar interlayer dielectric (ILD) disposed over one or more metallization level interconnecting a plurality of III-N HFETs into HFET circuitry.Type: GrantFiled: August 28, 2015Date of Patent: October 22, 2019Assignee: Intel CorporationInventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Ravi Pillarisetty, Kimin Jun, Patrick Morrow, Valluri R. Rao, Paul B. Fischer, Robert S. Chau
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Patent number: 10439134Abstract: Techniques are disclosed for forming non-planar resistive memory cells, such as non-planar resistive random-access memory (ReRAM or RRAM) cells. The techniques can be used to reduce forming voltage requirements and/or resistances involved (such as the resistance during the low-resistance state) relative to planar resistive memory cells for a given memory cell space. The non-planar resistive memory cell includes a first electrode, a second electrode, and a switching layer disposed between the first and second electrodes. The second electrode may be substantially between opposing portions of the switching layer, and the first electrode may be substantially adjacent to at least two sides of the switching layer, after the non-planar resistive memory cell is formed. In some cases, an oxygen exchange layer (OEL) may be disposed between the switching layer and one of the first and second electrodes to, for example, increase flexibility in incorporating materials in the cell.Type: GrantFiled: March 25, 2014Date of Patent: October 8, 2019Assignee: INTEL CORPORATIONInventors: Prashant Majhi, Elijah V. Karpov, Uday Shah, Niloy Mukherjee, Charles C. Kuo, Ravi Pillarisetty, Brian S. Doyle, Robert S. Chau
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Publication number: 20190287789Abstract: III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.Type: ApplicationFiled: June 4, 2019Publication date: September 19, 2019Applicant: Intel CorporationInventors: Sansaptak Dasgupta, Han Wui Then, Benjamin Chu-Kung, Marko Radosavljevic, Sanaz K. Gardner, Seung Hoon Sung, Ravi Pillarisetty, Robert S. Chau
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Patent number: 10418487Abstract: A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. A channel nanowire having a third lattice is formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. A gate dielectric layer is formed on and all-around the channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.Type: GrantFiled: November 19, 2015Date of Patent: September 17, 2019Assignee: Intel CorporationInventors: Willy Rachmady, Ravi Pillarisetty, Van H. Le, Jack T. Kavalieros, Robert S. Chau, Jessica S. Kachian
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Patent number: 10403811Abstract: A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.Type: GrantFiled: September 26, 2014Date of Patent: September 3, 2019Assignee: Intel CorporationInventors: Kevin P. O'Brien, Kaan Oguz, Brian S. Doyle, Mark L. Doczy, Charles C. Kuo, Robert S. Chau
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Patent number: 10395707Abstract: A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.Type: GrantFiled: September 26, 2014Date of Patent: August 27, 2019Assignee: Intel CorporationInventors: Mark L. Doczy, Kaan Oguz, Brian S. Doyle, Charles C. Kuo, Robert S. Chau, Satyarth Suri