Patents by Inventor Robert W. Wisniewski

Robert W. Wisniewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9971713
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Method and apparatus for a hierarchical synchronization barrier in a multi-node system
    Patent number: 9971635
    Abstract: A hierarchical barrier synchronization of cores and nodes on a multiprocessor system, in one aspect, may include providing by each of a plurality of threads on a chip, input bit signal to a respective bit in a register, in response to reaching a barrier; determining whether all of the plurality of threads reached the barrier by electrically tying bits of the register together and “AND”ing the input bit signals; determining whether only on-chip synchronization is needed or whether inter-node synchronization is needed; in response to determining that all of the plurality of threads on the chip reached the barrier, notifying the plurality of threads on the chip, if it is determined that only on-chip synchronization is needed; and after all of the plurality of threads on the chip reached the barrier, communicating the synchronization signal to outside of the chip, if it is determined that inter-node synchronization is needed.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Valentina Salapura, Robert W. Wisniewski
  • Methods and apparatus for managing and distinguishing instant messaging sessions and threads
    Patent number: 9805340
    Abstract: A method of managing instant messaging communication over a computer network is provided. One or more instant messaging session windows are organized in an instant messaging session manager. At least one distinguishing session characteristic is attributed to each of the one or more instant messaging session windows. The at least one distinguishing session characteristic is at least one of a sound clip associated with a user of the session, an instant messaging session window background associated with a user of the session, and a change in at least one of a color and an intensity of the instant messaging session window. The at least one distinguishing session characteristic increases a likelihood of identification of each of the one or more instant messaging session windows.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: October 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jarir Kamel Chaar, Neal Martin Keller, Clifford Alan Pickover, Robert W. Wisniewski
  • Virtual meetings
    Patent number: 9806894
    Abstract: A method for managing virtual meetings includes initiating participation with a first user interface in a first meeting, initiating participation with the first user interface in a second meeting, determining whether attention of a user is directed towards the first meeting or the second meeting, and configuring the user interface such that the user interacts with meeting resources associated with the first meeting responsive to determining that the attention of the user is directed towards the first meeting.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: October 31, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James R. Kozloski, Clifford A. Pickover, Robert W. Wisniewski
  • Virtual meetings
    Patent number: 9800422
    Abstract: A system for managing virtual meetings includes a processor operative to initiate participation with a first user interface in a first meeting, initiate participation with the first user interface in a second meeting, determining whether attention of a user is directed towards the first meeting or the second meeting, and configure the user interface such that the user interacts with meeting resources associated with the first meeting responsive to determining that the attention of the user is directed towards the first meeting.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: October 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James R. Kozloski, Clifford A. Pickover, Robert W. Wisniewski
  • Scalable synchronization mechanism for distributed memory
    Patent number: 9733995
    Abstract: A method comprising receiving control information at a first processing element from a second processing element, synchronizing objects within a shared global memory space of the first processing element with a shared global memory space of a second processing element in response to receiving the control information and generating a completion event indicating the first processing element has been synchronized with the second processing element.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Clement T. Cole, James Dinan, Gabriele Jost, Stanley C. Smith, Robert W. Wisniewski, Keith D. Underwood
  • Location-based vehicle powertrain regulation system
    Patent number: 9457797
    Abstract: A vehicle control system to control operation of a vehicle includes a powertrain system operable according to a plurality of operating modes that drive the vehicle. A sensor is mounted to the vehicle to detect a quality of air surrounding the vehicle. A vehicle control module is configured to select an operating mode of the powertrain system. The operating mode is selected to reduce at least one emission exhausted from the vehicle that contributes to a low air quality measure by the sensor.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: October 4, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James R. Kozloski, Clifford A. Pickover, Robert W. Wisniewski
  • Scalable Synchronization Mechanism for Distributed Memory
    Publication number: 20160179587
    Abstract: A method comprising receiving control information at a first processing element from a second processing element, synchronizing objects within a shared global memory space of the first processing element with a shared global memory space of a second processing element in response to receiving the control information and generating a completion event indicating the first processing element has been synchronized with the second processing element.
    Type: Application
    Filed: December 17, 2014
    Publication date: June 23, 2016
    Inventors: Clement T. Cole, James Dinan, Gabriele Jost, Stanley C. Smith, Robert W. Wisniewski, Keith D. Underwood
  • METHOD AND APPARATUS FOR A HIERARCHICAL SYNCHRONIZATION BARRIER IN A MULTI-NODE SYSTEM
    Publication number: 20160139965
    Abstract: A hierarchical barrier synchronization of cores and nodes on a multiprocessor system, in one aspect, may include providing by each of a plurality of threads on a chip, input bit signal to a respective bit in a register, in response to reaching a barrier; determining whether all of the plurality of threads reached the barrier by electrically tying bits of the register together and “AND”ing the input bit signals; determining whether only on-chip synchronization is needed or whether inter-node synchronization is needed; in response to determining that all of the plurality of threads on the chip reached the barrier, notifying the plurality of threads on the chip, if it is determined that only on-chip synchronization is needed; and after all of the plurality of threads on the chip reached the barrier, communicating the synchronization signal to outside of the chip, if it is determined that inter-node synchronization is needed.
    Type: Application
    Filed: January 26, 2016
    Publication date: May 19, 2016
    Inventors: Valentina Salapura, Robert W. Wisniewski
  • Method and apparatus for a hierarchical synchronization barrier in a multi-node system
    Patent number: 9286067
    Abstract: A hierarchical barrier synchronization of cores and nodes on a multiprocessor system, in one aspect, may include providing by each of a plurality of threads on a chip, input bit signal to a respective bit in a register, in response to reaching a barrier; determining whether all of the plurality of threads reached the barrier by electrically tying bits of the register together and “AND”ing the input bit signals; determining whether only on-chip synchronization is needed or whether inter-node synchronization is needed; in response to determining that all of the plurality of threads on the chip reached the barrier, notifying the plurality of threads on the chip, if it is determined that only on-chip synchronization is needed; and after all of the plurality of threads on the chip reached the barrier, communicating the synchronization signal to outside of the chip, if it is determined that inter-node synchronization is needed.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: March 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Valentina Salapura, Robert W. Wisniewski
  • MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
    Publication number: 20160011996
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Application
    Filed: April 30, 2015
    Publication date: January 14, 2016
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Method for guaranteeing program correctness using fine-grained hardware speculative execution
    Patent number: 9195550
    Abstract: A method for checking program correctness may include executing a program on a main hardware thread in speculative execution mode on a hardware execution context on a chip having a plurality of hardware execution contexts. In this mode, the main hardware thread's state is not committed to main memory. Correctness checks by a plurality of helper threads are executed in parallel to the main hardware thread. Each helper thread runs on a separate hardware execution context on the chip in parallel with the main hardware thread. The correctness checks determine a safe point in the program up to which the operations executed by the main hardware thread are correct. Once the main hardware thread reaches the safe point, the mode of execution of the main hardware thread is switched to non-speculative. The runtime then causes the main thread to re-enter speculative mode of execution.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: November 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Dan Tsafrir, Robert W. Wisniewski
  • Providing navigational support through corrective data
    Patent number: 9157755
    Abstract: A method and system for providing navigational support through corrective data includes monitoring a user's current position and travel pattern. A likelihood that the user is lost may be calculated based on the user's travel pattern and current position. If the likelihood exceeds a threshold value, the user may be provided with corrective data such as photographs or landmark information through visual or audio communication to assist the user in taking a corrective action or preventing getting lost.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: October 13, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James R. Kozloski, Clifford A. Pickover, Robert W. Wisniewski
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9081501
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: July 14, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Hardware enabled performance counters with support for operating system context switching
    Patent number: 9069891
    Abstract: A device for supporting hardware enabled performance counters with support for context switching include a plurality of performance counters operable to collect information associated with one or more computer system related activities, a first register operable to store a memory address, a second register operable to store a mode indication, and a state machine operable to read the second register and cause the plurality of performance counters to copy the information to memory area indicated by the memory address based on the mode indication.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: June 30, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Valentina Salapura, Robert W. Wisniewski
  • LOCATION-BASED VEHICLE POWERTRAIN REGULATION SYSTEM
    Publication number: 20150142243
    Abstract: A vehicle control system to control operation of a vehicle includes a powertrain system operable according to a plurality of operating modes that drive the vehicle. A sensor is mounted to the vehicle to detect a quality of air surrounding the vehicle. A vehicle control module is configured to select an operating mode of the powertrain system. The operating mode is selected to reduce at least one emission exhausted from the vehicle that contributes to a low air quality measure by the sensor.
    Type: Application
    Filed: January 28, 2015
    Publication date: May 21, 2015
    Inventors: James R. Kozloski, Clifford A. Pickover, Robert W. Wisniewski
  • Mechanisms for efficient intra-die/intra-chip collective messaging
    Patent number: 8990514
    Abstract: Mechanism of efficient intra-die collective processing across the nodelets with separate shared memory coherency domains is provided. An integrated circuit die may include a hardware collective unit implemented on the integrated circuit die. A plurality of cores on the integrated circuit die is grouped into a plurality of shared memory coherence domains. Each of the plurality of shared memory coherence domains is connected to the collective unit for performing collective operations between the plurality of shared memory coherence domains.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Amith R. Mamidala, Valentina Salapura, Robert W. Wisniewski
  • Location-based vehicle powertrain regulation system
    Patent number: 8972088
    Abstract: A vehicle control system to control operation of a vehicle includes a powertrain system operable according to a plurality of operating modes that drive the vehicle. A sensor is mounted to the vehicle to detect a quality of air surrounding the vehicle. A vehicle control module is configured to select an operating mode of the powertrain system. The operating mode is selected to reduce at least one emission exhausted from the vehicle that contributes to a low air quality measure by the sensor.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: James R. Kozloski, Clifford A. Pickover, Robert W. Wisniewski
  • Mechanism for optimized intra-die inter-nodelet messaging communication
    Patent number: 8943516
    Abstract: Point-to-point intra-nodelet messaging support for nodelets on a single chip that obey MPI semantics may be provided. In one aspect, a local buffering mechanism is employed that obeys standard communication protocols for the network communications between the nodelets integrated in a single chip. Sending messages from one nodelet to another nodelet on the same chip may be performed not via the network, but by exchanging messages in the point-to-point messaging buckets between the nodelets. The messaging buckets need not be part of the memory system of the nodelets. Specialized hardware controllers may be used for moving data between the nodelets and each messaging bucket, and ensuring correct operation of the network protocol.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Amith R. Mamidala, Valentina Salapura, Robert W. Wisniewski
  • PROVIDING NAVIGATIONAL SUPPORT THROUGH CORRECTIVE DATA
    Publication number: 20150019126
    Abstract: A method and system for providing navigational support through corrective data includes monitoring a user's current position and travel pattern. A likelihood that the user is lost may be calculated based on the user's travel pattern and current position. If the likelihood exceeds a threshold value, the user may be provided with corrective data such as photographs or landmark information through visual or audio communication to assist the user in taking a corrective action or preventing getting lost.
    Type: Application
    Filed: July 15, 2013
    Publication date: January 15, 2015
    Inventors: James R. Kozloski, Clifford A. Pickover, Robert W. Wisniewski