Patents by Inventor Robert W. Wisniewski

Robert W. Wisniewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory Architecture with Policy Based Data Storage
    Publication number: 20120066473
    Abstract: A computing system and methods for memory management are presented. A memory or an I/O controller receives a write request where the data two be written is associated with an address. Hint information may be associated with the address and may relate to memory characteristics such as an historical, O/S direction, data priority, job priority, job importance, job category, memory type, I/O sender ID, latency, power, write cost, or read cost components. The memory controller may interrogate the hint information to determine where (e.g., what memory type or class) to store the associated data. Data is therefore efficiently stored within the system. The hint information may also be used to track post-write information and may be interrogated to determine if a data migration should occur and to which new memory type or class the data should be moved.
    Type: Application
    Filed: September 15, 2010
    Publication date: March 15, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert B. Tremaine, Robert W. Wisniewski
  • MEMORY PAGE MANAGEMENT IN A TIERED MEMORY SYSTEM
    Publication number: 20120023300
    Abstract: Memory page management in a tiered memory system including a system that includes at least one page table for storing a plurality of entries, each entry associated with a page of memory and each entry including an address of the page and a memory tier of the page. The system also includes a control program configured for allocating pages associated with the entries to a software module, the allocated pages from at least two different memory tiers. The system further includes an agent of the control program capable of operating independently of the control program, the agent configured for receiving an authorization key to the allocated pages, and for migrating the allocated pages between the different memory tiers responsive to the authorization key.
    Type: Application
    Filed: July 26, 2010
    Publication date: January 26, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert B. Tremaine, Robert W. Wisniewski
  • Operating system thread scheduling for optimal heat dissipation
    Patent number: 8051276
    Abstract: A method and system for thread scheduling for optimal heat dissipation are provided. Temperature sensors measure temperature throughout various parts of a processor chip. The temperatures detected are reported to an operating system or the like for scheduling threads. In one aspect, the observed temperature values are recorded on registers. An operating system or the like reads the registers and schedules threads based on the temperature values.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: November 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Orran Y. Krieger, Bryan S. Rosenburg, Robert B. Tremaine, Robert W. Wisniewski
  • Message Passing with Queues and Channels
    Publication number: 20110246582
    Abstract: In an embodiment, a send thread receives an identifier that identifies a destination node and a pointer to data. The send thread creates a first send request in response to the receipt of the identifier and the data pointer. The send thread selects a selected channel from among a plurality of channels. The selected channel comprises a selected hand-off queue and an identification of a selected message unit. Each of the channels identifies a different message unit. The selected hand-off queue is randomly accessible. If the selected hand-off queue contains an available entry, the send thread adds the first send request to the selected hand-off queue. If the selected hand-off queue does not contain an available entry, the send thread removes a second send request from the selected hand-off queue and sends the second send request to the selected message unit.
    Type: Application
    Filed: March 30, 2010
    Publication date: October 6, 2011
    Applicant: International Business Machines Corporation
    Inventors: Gabor J. Dozsa, Philip Heidelberger, Sameer Kumar, Joseph D. Ratterman, Burkhard Steinmacher-Burow, Robert W. Wisniewski
  • MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
    Publication number: 20110219208
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).
    Type: Application
    Filed: January 10, 2011
    Publication date: September 8, 2011
    Applicant: International Business Machines Corporation
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • HARDWARE ENABLED PERFORMANCE COUNTERS WITH SUPPORT FOR OPERATING SYSTEM CONTEXT SWITCHING
    Publication number: 20110173503
    Abstract: A device for supporting hardware enabled performance counters with support for context switching include a plurality of performance counters operable to collect information associated with one or more computer system related activities, a first register operable to store a memory address, a second register operable to store a mode indication, and a state machine operable to read the second register and cause the plurality of performance counters to copy the information to memory area indicated by the memory address based on the mode indication.
    Type: Application
    Filed: January 8, 2010
    Publication date: July 14, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Valentina Salapura, Robert W. Wisniewski
  • HARDWARE SUPPORT FOR SOFTWARE CONTROLLED FAST MULTIPLEXING OF PERFORMANCE COUNTERS
    Publication number: 20110173588
    Abstract: Hardware support for software controlled fast multiplexing of performance counters may include a plurality of performance counters operable to collect one or more counts of one or more selected activities, and a plurality of registers operable to store a set of performance counter configurations. A state machine may be operable to automatically select a register from the plurality of registers for reconfiguring the one or more performance counters in response to receiving a first signal. The state machine may be further operable to reconfigure the one or more performance counters based on a configuration specified in the selected register. The state machine yet further may be operable to copy data in selected one or more of the plurality of performance counters to a memory location, or to copy data from the memory location to the counters, in response to receiving a second signal.
    Type: Application
    Filed: January 8, 2010
    Publication date: July 14, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Valentina Salapura, Robert W. Wisniewski
  • HARDWARE SUPPORT FOR COLLECTING PERFORMANCE COUNTERS DIRECTLY TO MEMORY
    Publication number: 20110173402
    Abstract: Hardware support for collecting performance counters directly to memory, in one aspect, may include a plurality of performance counters operable to collect one or more counts of one or more selected activities. A first storage element may be operable to store an address of a memory location. A second storage element may be operable to store a value indicating whether the hardware should begin copying. A state machine may be operable to detect the value in the second storage element and trigger hardware copying of data in selected one or more of the plurality of performance counters to the memory location whose address is stored in the first storage element.
    Type: Application
    Filed: January 8, 2010
    Publication date: July 14, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan Gara, Valentina Salapura, Robert W. Wisniewski
  • HARDWARE SUPPORT FOR SOFTWARE CONTROLLED FAST RECONFIGURATION OF PERFORMANCE COUNTERS
    Publication number: 20110173431
    Abstract: Hardware support for software controlled reconfiguration of performance counters may include a plurality of performance counters collecting one or more counts of one or more selected activities. A storage element stores data value representing a time interval, and a timer element reads the data value and detects expiration of the time interval based on the data value and generates a signal. A plurality of configuration registers stores a set of performance counter configurations. A state machine receives the signal and selects a configuration register from the plurality of configuration registers for reconfiguring the one or more performance counters.
    Type: Application
    Filed: January 8, 2010
    Publication date: July 14, 2011
    Applicant: International Business Machines Corporation
    Inventors: Valentina Salapura, Robert W. Wisniewski
  • USING DMA FOR COPYING PERFORMANCE COUNTER DATA TO MEMORY
    Publication number: 20110173403
    Abstract: A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data.
    Type: Application
    Filed: January 8, 2010
    Publication date: July 14, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan Gara, Valentina Salapura, Robert W. Wisniewski
  • Combined Memory Including a Logical Partition in a Storage Memory Accessed Through an IO Controller
    Publication number: 20110161597
    Abstract: A computer system having a combined memory. A first logical partition of the combined memory is a main memory region in a storage memory. A second logical partition of the combined memory is a direct memory region in a main memory. A memory controller comprising a storage controller is configured to receive a memory access request including a real address from a processor, determine whether the real address is for the first logical partition or for the second logical partition. If the address is for the first logical partition the storage controller communicates with an IO controller in the storage memory to service the memory access request. If the address is for the direct memory region, the memory controller services the memory access request in a conventional manner.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert B. Tremaine, Robert W. Wisniewski
  • Scheduling for functional units on simultaneous multi-threaded processors
    Publication number: 20110126200
    Abstract: A method and system for scheduling threads on simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system determines thread scheduling based on the information.
    Type: Application
    Filed: July 19, 2006
    Publication date: May 26, 2011
    Applicant: International Business Machine Corporation
    Inventors: Orran Y. Krieger, Bryan S. Rosenburg, Balaram Sinharoy, Robert B. Tremaine, Robert W. Wisniewski
  • CACHE RECONFIGURATION BASED ON RUN-TIME PERFORMANCE DATA OR SOFTWARE HINT
    Publication number: 20110107032
    Abstract: A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.
    Type: Application
    Filed: January 6, 2011
    Publication date: May 5, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xiaowei Shen, Balaram Sinharoy, Robert B. Tremaine, Robert W. Wisniewski
  • Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hint
    Patent number: 7913041
    Abstract: A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: March 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Xiaowei Shen, Balaram Sinharoy, Robert B. Tremaine, Robert W. Wisniewski
  • Color-based cache monitoring
    Patent number: 7895392
    Abstract: Color-based caching allows each cache line to be distinguished by a specific color, and enables the manipulation of cache behavior based upon the colors of the cache lines. When multiple threads are able to share a cache, effective cache management is critical to overall performance. Color-based caching provides an effective method to better utilize a cache and avoid unnecessary cache thrashing and/or pollution. The color based caching can be monitored to improve memory performance and guarantee Quality-Of-Service of cache utilization.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: February 22, 2011
    Assignee: International Business Machines
    Inventors: Xiaowei Shen, David F. Bacon, Robert W. Wisniewski, Orran Krieger
  • System and method for networking educational equipment
    Patent number: 7870252
    Abstract: A system, method and computer program product for monitoring availability of end user devices needed for performing tasks. The system comprises a first network including one or more devices associated with an end user, at least one device adapted for communicating with a service provider over a second network, the service provider providing network-based services in the system. The system includes a memory storage device for maintaining information of tasks associated with an end user, the information including recommended end-user devices adapted to perform the tasks, the information being accessible to at least one end-user device. At least one end-user device detects non-availability or performance deficiencies of any end-user device required in performing end-user tasks, and communicates with the service provider for invoking network-based services to facilitate correcting non-availability of any end-user device.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: January 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Neal Keller, Juhnyoung Lee, Clifford A. Pickover, Robert W. Wisniewski
  • Intelligent cache replacement mechanism with varying and adaptive temporal residency requirements
    Patent number: 7844778
    Abstract: A method for replacing cached data is disclosed. The method in one aspect associates an importance value to each block of data in the cache. When a new entry needs to be stored in the cache, a cache block for replacing is selected based on the importance values associated with cache blocks. In another aspect, the importance values are set according to the hardware and/or software's knowledge of the memory access patterns. The method in one aspect may also include varying the importance value over time over different processing requirements.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: November 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: Xiaowei Shen, Balaram Sinharoy, Robert W. Wisniewski
  • INTELLIGENT CACHE REPLACEMENT MECHANISM WITH VARYING AND ADAPTIVE TEMPORAL RESIDENCY REQUIREMENTS
    Publication number: 20100281218
    Abstract: A method for replacing cached data is disclosed. The method in one aspect associates an importance value to each block of data in the cache. When a new entry needs to be stored in the cache, a cache block for replacing is selected based on the importance values associated with cache blocks. In another aspect, the importance values are set according to the hardware and/or software's knowledge of the memory access patterns. The method in one aspect may also include varying the importance value over time over different processing requirements.
    Type: Application
    Filed: July 11, 2006
    Publication date: November 4, 2010
    Applicant: International Business Machines Corporation
    Inventors: Xiaowei Shen, Balaram Sinharoy, Robert W. Wisniewski
  • Prefetch engine based translation prefetching
    Publication number: 20100250853
    Abstract: A method and system for prefetching in computer system are provided. The method in one aspect includes using a prefetch engine to perform prefetch instructions and to translate unmapped data. Misses to address translations during the prefetch are handled and resolved. The method also includes storing the resolved translations in a respective cache translation table. A system for prefetching in one aspect includes a prefetch engine operable to receive instructions to prefetch data from the main memory. The prefetch engine is also operable to search cache address translation for prefetch data and perform address mapping translation, if the prefetch data is unmapped. The prefetch engine is further operable to prefetch the data and store the address mapping in one or more cache memory, if the data is unmapped.
    Type: Application
    Filed: July 7, 2006
    Publication date: September 30, 2010
    Applicant: International Business Machines Corporation
    Inventors: Orran Y. Krieger, Balaram Sinharoy, Robert B. Tremaine, Robert W. Wisniewski
  • Mechanism to save and restore cache and translation trace for fast context switch
    Patent number: 7634642
    Abstract: A method and system for efficient context switching are provided. An execution entity that is to be context switched out is allowed to continue executing for a predetermined period of time before being context switched out. During the predetermined period of time in which the execution entity continues to execute, the hardware or an operating system tracks and records its footprint such as the addresses and page and segment table entries and the like accessed by the continued execution. When the execution entity is being context switched back in, its page and segment table and cache states are reloaded for use in its immediate execution.
    Type: Grant
    Filed: July 6, 2006
    Date of Patent: December 15, 2009
    Assignee: International Business Machines Corporation
    Inventors: Peter H. Hochschild, Xiaowei Shen, Balaram Sinharoy, Robert W. Wisniewski