Abstract: A method for vertical integrated performance and environment monitoring includes steps, or acts, of: defining one or more events to provide a unified specification; registering one or more events to be detected; detecting an occurrence of at least one of the registered event or events; generating a monitoring entry each time one of the registered events is detected; and entering each of the monitoring entries generated into a single logical entity.

Abstract: A system and method for latency-aware thread scheduling in non-uniform cache architecture are provided. Instructions may be provided to the hardware specifying in which banks to store data. Information as to which banks store which data may also be provided, for example, by the hardware. This information may be used to schedule threads on one or more cores. A selected bank in cache memory may be reserved strictly for selected data.

Abstract: A system and method for latency-aware thread scheduling in non-uniform cache architecture are provided. Instructions may be provided to the hardware specifying in which banks to store data. Information as to which banks store which data may also be provided, for example, by the hardware. This information may be used to schedule threads on one or more cores. A selected bank in cache memory may be reserved strictly for selected data.

Abstract: A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.

Abstract: A system and method for mapping application tasks to processors in a computing environment that takes into account the hardware communication topology of a machine and an application communication pattern. The hardware communication topology (HCT) is defined according to hardware parameters affecting communication between two tasks, such as connectivity, bandwidth and latency; and, the application communication pattern (ACP) is defined to mean the number and size of bytes that are communicated between the different pairs of communicating tasks. By collecting information on the messages exchanged by the tasks that communicate, the communication pattern of the application may be determined. By combing the HCT and ACP a cost model for a given mapping can be determined.

Abstract: A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.

Abstract: A method and system for providing quality of service guarantees for simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system controls scheduling of the threads based at least partly on the information communicated and provides quality of service guarantees.

Abstract: A method of managing instant messaging communication over a computer network is provided. One or more instant messaging session windows are organized in an instant messaging session manager. At least one distinguishing session characteristic is attributed to each of the one or more instant messaging session windows. The at least one distinguishing session characteristic is at least one of a sound clip associated with a user of the session, an instant messaging session window background associated with a user of the session, and a change in at least one of a color and an intensity of the instant messaging session window. The at least one distinguishing session characteristic increases a likelihood of identification of each of the one or more instant messaging session windows.

Abstract: Color-based caching allows each cache line to be distinguished by a specific color, and enables the manipulation of cache behavior based upon the colors of the cache lines. When multiple threads are able to share a cache, effective cache management is critical to overall performance. Color-based caching provides an effective method to better utilize a cache and avoid unnecessary cache thrashing and/or pollution. The color based caching can be monitored to improve memory performance and guarantee Quality-Of-Service of cache utilization.

Abstract: Color-based caching allows each cache line to be distinguished by a specific color, and enables the manipulation of cache behavior based upon the colors of the cache lines. When multiple threads are able to share a cache, effective cache management is critical to overall performance. Color-based caching provides an effective method to better utilize caches and avoid unnecessary cache thrashing and pollution. Hardware maintains color-based counters relative to the cache lines to monitor and obtain feedback on cache line events. These counters are utilized for cache coherence transactions in multiple processor systems.

Abstract: Memory Access Coloring provides architecture support that allows software to classify memory accesses into different congruence classes by specifying a color for each memory access operation. The color information is received and recorded by the underlying system with appropriate granularity. This allows hardware to monitor color-based cache monitoring information and provide such feedback to the software to enable various runtime optimizations. It also enables enforcement of different memory consistency models for memory regions with different colors at the same time.

Abstract: A method for modeling the performance of memory address translation mechanism (MATM), comprises: a) receiving an execution profile that contains a memory address reference stream of an application, a set of page size mappings, and events about the application's data allocations and de-allocations; b) translating each memory reference in the input memory reference stream into a reference to the corresponding data object, by consulting the memory allocation and de-allocation events, to provide a data object reference stream; c) translating each data object reference into a corresponding page reference by consulting the page size mapping and by modeling the data allocation and de-allocation events in accordance with the mapping to provide a page reference stream and a number of pages of each page size that are needed by the respective mapping; d) using the page reference stream to provide a stream of reuse distance values; e) determining, for each reference in the reuse distance value stream, whether the referen

Abstract: In the context of screens, windows and like media, arrangements for automatically detecting when a recipient has entered or left a public setting so that privacy configuration changes can be automatically invoked. Also broadly contemplated herein is an arrangement for selectively displaying messages on the recipient's screen but deferring the messages from being visible on a remote hardware device or software display which is publicly visible. Furthermore, there is broadly contemplated herein a secure arrangement for revealing and responding to deferred messages. More generally, there is broadly contemplated herein a new approach to the provision of application notifications and to alarm control during a desktop screen sharing mode, based on the automatic detection of a screen sharing state and on notifying registered applications of the screen sharing in a unified, consistent manner.

Abstract: A method and system for thread scheduling for optimal heat dissipation are provided. Temperature sensors measure temperature throughout various parts of a processor chip. The temperatures detected are reported to an operating system or the like for scheduling threads. In one aspect, the observed temperature values are recorded on registers. An operating system or the like reads the registers and schedules threads based on the temperature values.

Abstract: A method and system for providing quality of service guarantees for simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system controls scheduling of the threads based at least partly on the information communicated and provides quality of service guarantees.

Abstract: A method and system for efficient context switching are provided. An execution entity that is to be context switched out is allowed to continue executing for a predetermined period of time before being context switched out. During the predetermined period of time in which the execution entity continues to execute, the hardware or an operating system tracks and records its footprint such as the addresses and page and segment table entries and the like accessed by the continued execution. When the execution entity is being context switched back in, its page and segment table and cache states are reloaded for use in its immediate execution.

Abstract: A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.

Abstract: A method for allowing a system programmer using a computing system to efficiently use a queuing lock without the requirement of pre-allocating qnode structures for each possible thread of computation expecting to use the lock. More specifically, the lock structure of this invention uses two pointers: a head pointer that points to the next qnode structure representing the next thread or process interested in acquiring the lock, and a tail pointer pointing to the qnode structure representing the last thread or process in a queue of threads or processes awaiting to acquire the lock. When the lock is released, a flag is changed in the qnode structure of the next thread in line (pointed to by the head of the lock) indicating that thread now has the lock and may proceed. A thread or process obtains the lock by spinning on a flag in a qnode structure representing such thread or process.