Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include anon-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

Abstract: Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

Abstract: Methods for forming dual damascene structures in low-k dielectric materials that facilitate reducing photoresist poison issues are provided herein. In some embodiments, such methods may include plasma etching a via through a first mask layer into a low-k dielectric material disposed on a substrate. The first mask layer may then be removed using a process including exposing the first mask layer to a first plasma comprising an oxygen containing gas and at least one of a dilutant gas or a passivation gas, and subsequently exposing the first mask layer to a second plasma comprising an oxygen containing gas and formed using one of either plasma bias power or plasma source power. An anti-reflective coating may then be deposited into the via and atop the low-k dielectric material. A trench may then be plasma etched through a second mask layer formed atop the anti-reflective coating into the low-k dielectric material.

Abstract: The present invention provides methods and apparatus for predictive maintenance of semiconductor process equipment. In some embodiments, a method for performing predictive maintenance on semiconductor processing equipment includes performing at least one self-diagnostic test on the semiconductor processing equipment with no substrate present in the equipment; comparing a result of the at least one self diagnostic test to at least one baseline characterization of the equipment; and determining whether equipment maintenance is required based upon the comparison.

Abstract: The present invention provides an electro-chemical deposition system that is designed with a flexible architecture that is expandable to accommodate future designs and gap fill requirements and provides satisfactory throughput to meet the demands of other processing systems. The electro-chemical deposition system generally comprises a mainframe having a mainframe wafer transfer robot, a loading station disposed in connection with the mainframe, one or more processing cells disposed in connection with the mainframe, and an electrolyte supply fluidly connected to the one or more electrical processing cells. Preferably, the electro-chemical deposition system includes a spin-rinse-dry (SRD) station disposed between the loading station and the mainframe, a rapid thermal anneal chamber attached to the loading station, and a system controller for controlling the electro-chemical deposition process and the components of the electro-chemical deposition system.

Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

Abstract: Methods for post-etch deposition on a dielectric film are provided in the present invention. In one embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in a etch reactor, etching the low-k dielectric layer in the etch reactor, and forming a protection layer on the etched low-k dielectric layer. In another embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in an etch reactor, etching the low-k dielectric layer in the reactor, bonding the etched low-k dielectric layer with a polymer gas supplied into the reactor, forming a protection layer on the etched low-k dielectric layer, and removing the protection layer formed on the etched low-k dielectric layer.

Abstract: A semiconductor stack having a protective layer formed into a low k dielectric material is provided. The method for forming the protective layer in a low k dielectric material may include plasma etching the low k dielectric material to form Si—OH bonds on a surface of the low k dielectric material, exposing the Si—OH bonds to a silicon containing fluid solution, and replacing the Si—OH bonds with Si—Si bonds generated by the silicon containing fluid solution to form a protective layer on the surface of the low k dielectric material.

Abstract: Methods for post-etch deposition on a dielectric film are provided in the present invention. In one embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in a etch reactor, etching the low-k dielectric layer in the etch reactor, and forming a protection layer on the etched low-k dielectric layer. In another embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in an etch reactor, etching the low-k dielectric layer in the reactor, bonding the etched low-k dielectric layer with a polymer gas supplied into the reactor, forming a protection layer on the etched low-k dielectric layer, and removing the protection layer formed on the etched low-k dielectric layer.

Abstract: A method and apparatus for annealing copper. The method comprises forming a copper layer by electroplating on a substrate in an integrated processing system and annealing the copper layer in a chamber inside the integrated processing system.

Abstract: A method and apparatus for annealing copper. The method comprises forming a copper layer by electroplating on a substrate in an integrated processing system and annealing the copper layer in a chamber inside the integrated processing system.

Abstract: The present invention provides an electro-chemical deposition system that is designed with a flexible architecture that is expandable to accommodate future designs and gap fill requirements and provides satisfactory throughput to meet the demands of other processing systems. The electro-chemical deposition system generally comprises a mainframe having a mainframe wafer transfer robot, a loading station disposed in connection with the mainframe, one or more processing cells disposed in connection with the mainframe, and an electrolyte supply fluidly connected to the one or more electrical processing cells. Preferably, the electro-chemical deposition system includes a spin-rinse-dry (SRD) station disposed between the loading station and the mainframe, a rapid thermal anneal chamber attached to the loading station, and a system controller for controlling the electro-chemical deposition process and the components of the electro-chemical deposition system.

Abstract: An apparatus for performing intra-tool monitoring and control within a multi-step processing system. The apparatus provides a metrology station located between each of a plurality of semiconductor wafer processing tools such that measurements can be made on wafers as they are passed from one tool to another providing intra tool monitoring. The data collected by the metrology station is coupled to a metrology data analyzer, which determines whether any of the plurality of wafer processing tools should be adjusted to improve the processing of the overall wafer. As such, the output of the metrology data analyzer provides control parameters to process controllers connected controllers connected to each of the tools within the semiconductor wafer processing system. Consequently, the operation of the metrology stations and the metrology data analyzer provides both feed forward and feed back data to control the tools based upon certain information that is gathered within the metrology station.

Abstract: A method and apparatus for performing intra-tool monitoring and control within a multi-step processing system. The method monitors the processing of a workpiece as the workpiece is processed by independently operating processing tools and produces control parameters for the various independently operating processing tools to optimize the processing of the workpiece. More specifically, the apparatus provides a metrology station located between each of a plurality of semiconductor wafer processing tools such that measurements can be made on wafers as they are passed from one tool to another providing intra tool monitoring. The data collected by the metrology station is coupled to a metrology data analyzer, which determines whether any of the plurality of wafer processing tools should be adjusted to improve the processing of the overall wafer.

Abstract: The present invention provides methods for fabricating integrated circuit structures for use in semiconductor wafer fabrication techniques. A Cu diffusion barrier/Cu seed sandwich layer is deposited on a substrate. A first sacrificial layer, deposited on the sandwich layer, is developed to form a cavity. A first Cu layer is selectively deposited on the sandwich layer inside the cavity. A second sacrificial layer is deposited on the first sacrificial layer and on the first Cu layer. A cavity is formed in the second sacrificial layer, exposing at least a portion of the first Cu layer. A second Cu layer is selectively deposited in the second sacrificial layer cavity including the exposed portion of the first Cu layer. The combination of the first and second Cu layers forms a Cu component. Subsequently, the first and second sacrificial layers are removed resulting in a Cu component that is free standing on the sandwich layer, such that the top and sides of the component are exposed.

Abstract: A method and apparatus for heating and cooling a substrate are provided. A chamber is provided that comprises a heating mechanism adapted to heat a substrate positioned proximate the heating mechanism, a cooling mechanism spaced from the heating mechanism and adapted to cool a substrate positioned proximate the cooling mechanism, and a transfer mechanism adapted to transfer a substrate between the position proximate the heating mechanism and the position proximate the cooling mechanism.