Abstract: A sensor comprising a silicon substrate having a first and a second surface, integrated circuitry provided on the first surface of the silicon substrate, and a sensor structure provided on the second surface of the silicon substrate. The sensor structure and the integrated circuitry are electrically coupled to each other.

Abstract: Disclosed is an integrated circuit (IC) comprising a substrate (10) including a plurality of circuit elements and a metallization stack (20) covering said substrate for providing interconnections between the circuit elements, wherein the top metallization layer of said stack carries a plurality of metal portions (30) embedded in an exposed porous material (40) for retaining a liquid, said porous material laterally separating said plurality of metal portions. An electronic device comprising such an IC and a method of manufacturing such an IC are also disclosed.

Abstract: A method of forming an interconnect structure in a semiconductor device in which via holes (62) defined in a dielectric layer are filled with a filler material (64), such as a porogen material, before a further dielectric layer (66) is deposited thereover. Trenches (72) are formed in the further dielectric layer and then the filler material exposed thereby in the via holes is removed. The method provides a robust process which affords improved via and trench profile control.

Abstract: An electric device has an electrically switchable resistor (2?) comprising a phase change material. The resistance value of the resistor can be changed between at least two values by changing the phase of the phase change material within a part of the resistor called the switching zone (12?) using Joule heating of the resistor. The device comprises a body (24?) encapsulating the resistor, which body comprises at least two abutting regions (26?, 28?) having different thermally insulating properties. These regions form a thermally insulating contrast with which the dimension of the switching zone can be determined without having to alter the dimensions of the resistor. Such a device can be used in electronic memory or reconfigurable logic circuits.

Abstract: The method of manufacturing an integrated circuit (IC) according to the invention starts with providing a pre-fabricated integrated circuit (10) comprising an electrical device (2) and having a surface (11) coated with a dielectric material (12) and a metal (15). The dielectric material (12), which may be separated from the metal (15) by the barrier layer (14), has an opening (13), which is filled with the metal (15). Portions of the metal (15) outside the opening (13) are removed by polishing for a first period of time, after which an etching agent (25) is added to the polishing liquid (24) and polishing is continued for a second period of time for removing portions of the metal (15) remaining outside the opening (13). The polishing apparatus (40) is able to perform the method.

Abstract: A method of forming an interconnect structure in a semiconductor device in which via holes (62) defined in a dielectric layer are filled with a filler material (64), such as a porogen material, before a further dielectric layer (66) is deposited thereover. Trenches (72) are formed in the further dielectric layer and then the filler material exposed thereby in the via holes is removed. The method provides a robust process which affords improved via and trench profile control.

Abstract: A damascene process is described using a copper fill process to fill a trench (12). The copper fill (20) is started with a deposited seed layer which includes (5) copper and titanium. Some titanium migrates to the surface during the copper fill process. The structure is annealed in a nitrogen atmosphere which creates a self-aligned TiN barrier (24) at the surface of the copper fill (20). Air gaps (26) may be created in the same annealing process. The process may be used to form a multilayer structure.

Abstract: A method of packaging a micro electromechanical structure is disclosed. The method comprises the steps of forming the structure on a substrate, depositing a sacrificial layer over the structure, patterning the sacrificial layer, depositing a porous layer over the patterned sacrificial layer, removing the patterned sacrificial layer through the porous layer, treating the porous layer with a plasma and depositing a capping layer over the plasma-treated porous layer. The plasma treatment step ensures that the capping layer material cannot enter the cavity formed by the removal of the sacrificial layer through the porous layer. A device formed by this method is also disclosed.

Abstract: The invention relates to a micro-device with a cavity (50), the micro-device comprising a substrate (10, 110), the method comprising steps of: A) providing the substrate (10, 110), having a surface and comprising a sacrificial oxide region (20, 107, 115) at the surface ( ); B) covering the sacrificial oxide region (20, 107, 115) with a porous layer (40, 114, 124) being permeable to a vapor HF etchant (100), and C) selectively etching the sacrificial oxide region (20, 107, 115) through the porous layer (40, 114, 124) using the vapor HF etchant (100) to obtain the cavity (50). This method may be used in the manufacture of various micro-devices with a cavity (50), i.e. MEMS devices, and in particular in the encapsulation part thereof, and semiconductor devices, and in particular the BEOL-part thereof.

Abstract: A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises providing a substantially planar layer having a first metal layer, depositing a via level dielectric layer, patterning the via level dielectric layer, at least partly etching the via level dielectric layer, depositing a disposable layer on the at least partly etched via level dielectric layer, patterning the disposable layer, depositing a second metal layer, planarizing second metal layer, depositing permeable dielectric layer after planarizing the second metal layer, and removing the disposable layer through the permeable dielectric layer to form air gaps.

Abstract: An electric device has an electrically switchable resistor (2?) comprising a phase change material. The resistance value of the resistor can be changed between at least two values by changing the phase of the phase change material within a part of the resistor called the switching zone (12?) using Joule heating of the resistor. The device comprises a body (24?) encapsulating the resistor, which body comprises at least two abutting regions (26?, 28?) having different thermally insulating properties. These regions form a thermally insulating contrast with which the dimension of the switching zone can be determined without having to alter the dimensions of the resistor. Such a device can be used in electronic memory or reconfigurable logic circuits.

Abstract: A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises the steps of depositing and patterning a disposable layer, depositing a first barrier layer on top of the patterned disposable layer, depositing a metal layer, planarizing the metal layer, depositing a second barrier layer, planarizing the second barrier layer until substantially no barrier layer material is present on top of the disposable layer, depositing a permeable layer, removing the disposable layer through the permeable layer to form air gaps.

Abstract: A method to produce air gaps between metal lines (8(i)( and within dielectrics. The method consists of obtaining a dual damascene structure, applying a diffusion barrier layer (10) directly on the planarized surface and performing a lithography step, thus shielding the metal lines underneath the diffusion barrier layer. Optionally, some portions of large dielectric areas (6) between the metal lines (8(i)) are also shielded. The exposed diffusion barrier layer portions and underlying dielectric are etched. A layer of a material that can be decomposed in volatile components by heating to a temperature of typically between 150-450° C. is applied and planarized by etching or CMP. A dielectric layer (20) that is permeable to the decomposition products is deposited and subsequently the substrate is heated. Then, the disposable layer decomposes and disappears through the permeable dielectric layer, leaving air gaps (22) behind in between the metal lines (8(i)) and the large dielectric areas.

Abstract: The method of manufacturing an integrated circuit (IC) according to the invention starts with providing a pre-fabricated integrated circuit (10) comprising an electrical device (2) and having a surface (11) coated with a dielectric material (12) and a metal (15). The dielectric material (12), which may be separated from the metal (15) by the barrier layer (14), has an opening (13), which is filled with the metal (15). Portions of the metal (15) outside the opening (13) are removed by polishing for a first period of time, after which an etching agent (25) is added to the polishing liquid (24) and polishing is continued for a second period of time for removing portions of the metal (15) remaining outside the opening (13). The polishing apparatus (40) is able to perform the method.

Abstract: A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises providing a substantially planar layer having a first metal layer, depositing a via level dielectric layer, patterning the via level dielectric layer, at least partly etching the via level dielectric layer, depositing a disposable layer on the at least partly etched via level dielectric layer, patterning the disposable layer, depositing a second metal layer, planarizing second metal layer, depositing permeable dielectric layer after planarizing the second metal layer, and removing the disposable layer through the permeable dielectric layer to form air gaps.

Abstract: A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises the steps of depositing and patterning a disposable layer, depositing a first barrier layer on top of the patterned disposable layer, depositing a metal layer, planarizing the metal layer, depositing a second barrier layer, planarizing the second barrier layer until substantially no barrier layer material is present on top of the disposable layer, depositing a permeable layer, removing the disposable layer through the permeable layer to form air gaps.