Patents by Inventor Roger A. Quon
Roger A. Quon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070084629Abstract: Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.Type: ApplicationFiled: October 5, 2006Publication date: April 19, 2007Inventors: William Bernier, Marie Cole, Mukta Farooq, John Knickerbocker, Tasha Lopez, Roger Quon, David Welsh
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Publication number: 20070080455Abstract: A semiconductor having an insulating layer, a contact pad, a via, and a sacrificial dielectric cap is provided. The contact pad is embedded in the insulating layer, where the contact pad has a top metal layer of copper. The via creates an opening over the top metal layer. The sacrificial dielectric cap is over at least the top metal layer.Type: ApplicationFiled: October 11, 2005Publication date: April 12, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Donna Zupanski-Nielsen, William Landers, Ian Melville, Roger Quon, Timothy Daubenspeck, Kamalesh Srivastava, Mary Cullinan-Scholl, Lawrence Clevenger, Christopher Muzzy
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Patent number: 7170187Abstract: Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.Type: GrantFiled: August 31, 2004Date of Patent: January 30, 2007Assignee: International Business Machines CorporationInventors: William E. Bernier, Marie S. Cole, Mukta G. Farooq, John U. Knickerbocker, Tasha E. Lopez, Roger A. Quon, David J. Welsh
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Patent number: 7144490Abstract: A method for selective electroplating of a semiconductor input/output (I/O) pad includes forming a titanium-tungsten (TiW) layer over a passivation layer on a semiconductor substrate, the TiW layer further extending into an opening formed in the passivation layer for exposing the I/O pad, such that the TiW layer covers sidewalls of the opening and a top surface of the I/O pad. A seed layer is formed over the TiW layer, and portions of the seed layer are selectively removed such that remaining seed layer material corresponds to a desired location of interconnect metallurgy for the I/O pad. At least one metal layer is electroplated over the remaining seed layer material, using the TiW layer as a conductive electroplating medium.Type: GrantFiled: November 18, 2003Date of Patent: December 5, 2006Assignee: International Business Machines CorporationInventors: Tien-Jen Cheng, David E. Eichstadt, Jonathan H. Griffith, Sarah H. Knickerbocker, Rosemary A. Previti-Kelly, Roger A. Quon, Kamalesh K. Srivastava, Keith Kwong-Hon Wong
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Publication number: 20060249854Abstract: A durable chip pad for integrated circuit (IC) chips, semiconductor wafer with IC chips with durable chip pads in a number of die locations and a method of making the IC chips on the wafer. The chip may be probed for performance testing with the probe contacting the durable chip pads directly.Type: ApplicationFiled: June 29, 2006Publication date: November 9, 2006Inventors: Tien-Jen Cheng, David Eichstadt, Jonathan Griffith, Sarah Knickerbocker, Samuel McKnight, Kevin Petrarca, Kamalesh Srivastava, Roger Quon
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Publication number: 20060211167Abstract: Disclosed are microelectronic structures based on improved design and material combinations to provide improved current capabilities per I/O. The preferred embodiment of the invention uses a combination of one or more of the following: (1) Underbump metallurgy which enhances current per I/O by increasing via diameter or by having multiple via openings under BLM; (2) Thicker underbump metallurgy, where use of good conductor metallurgies can be used with increased thickness; (3) Utilizing larger via diameter under bump metallurgy, larger solder bump diameter and/or other current enhancing features for power and/or ground via connections; and (4) Using additives in Pb-free alloys to alter microstructure to minimize migration of atoms in the solder or at intermetallic transitions.Type: ApplicationFiled: March 18, 2005Publication date: September 21, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Knickerbocker, Hai Longworth, Roger Quon
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Publication number: 20060081981Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.Type: ApplicationFiled: November 10, 2005Publication date: April 20, 2006Applicant: International Business Machines CorporationInventors: Julie Biggs, Tien-Jen Cheng, David Eichstadt, Lisa Fanti, Jonathan Griffith, Randolph Knarr, Sarah Knickerbocker, Kevin Petrarca, Roger Quon, Wolfgang Sauter, Kamalesh Srivastava, Richard Volant
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Publication number: 20060043608Abstract: Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.Type: ApplicationFiled: August 31, 2004Publication date: March 2, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William Bernier, Marie Cole, Mukta Farooq, John Knickerbocker, Tasha Lopez, Roger Quon, David Welsh
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Patent number: 6995475Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.Type: GrantFiled: September 18, 2003Date of Patent: February 7, 2006Assignee: International Business Machines CorporationInventors: Julie C. Biggs, Tien-Jen Cheng, David E. Eichstadt, Lisa A. Fanti, Jonathan H. Griffith, Randolph F. Knarr, Sarah H. Knickerbocker, Kevin S. Petrarca, Roger A. Quon, Wolfgang Sauter, Kamalesh K. Srivastava, Richard P. Volant
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Patent number: 6995084Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.Type: GrantFiled: March 17, 2004Date of Patent: February 7, 2006Assignee: International Business Machines CorporationInventors: Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, Roger A. Quon, William E. Sablinski, Julie C. Biggs, David E. Eichstadt, Jonathan H. Griffith
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Patent number: 6992389Abstract: A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.Type: GrantFiled: April 28, 2004Date of Patent: January 31, 2006Assignee: International Business Machines CorporationInventors: Panayotis C. Andricacos, Tien-Jen J. Cheng, Emanuel I. Cooper, David E. Eichstadt, Jonathan H. Griffith, Randolph F. Knarr, Roger A. Quon, Erik J. Roggeman
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Publication number: 20060009022Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.Type: ApplicationFiled: September 12, 2005Publication date: January 12, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kamalesh Srivastava, Subhash Shinde, Tien-Jen Cheng, Sarah Knickerbocker, Roger Quon, William Sablinski, Julie Biggs, David Eichstadt, Jonathan Griffith
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Publication number: 20050245070Abstract: A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.Type: ApplicationFiled: April 28, 2004Publication date: November 3, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Panayotis Andricacos, Tien-Jen Cheng, Emanuel Cooper, David Eichstadt, Jonathan Griffith, Randolph Knarr, Roger Quon, Erik Roggeman
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Publication number: 20050208748Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.Type: ApplicationFiled: March 17, 2004Publication date: September 22, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kamalesh Srivastava, Subhash Shinde, Tien-Jen Cheng, Sarah Knickerbocker, Roger Quon, William Sablinski, Julie Biggs, David Eichstadt, Jonathan Griffith
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Publication number: 20050167837Abstract: A durable chip pad for integrated circuit (IC) chips, semiconductor wafer with IC chips with durable chip pads in a number of die locations and a method of making the IC chips on the wafer. The chip may be probed for performance testing with the probe contacting the durable chip pads directly.Type: ApplicationFiled: January 21, 2004Publication date: August 4, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tien-Jen Cheng, David Eichstadt, Jonathan Griffith, Sarah Knickerbocker, Samuel McKnight, Kevin Petrarca, Kamalesh Srivastava, Roger Quon
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Publication number: 20050103636Abstract: A method for selective electroplating of a semiconductor input/output (I/O) pad includes forming a titanium-tungsten (TiW) layer over a passivation layer on a semiconductor substrate, the TiW layer further extending into an opening formed in the passivation layer for exposing the I/O pad, such that the TiW layer covers sidewalls of the opening and a top surface of the I/O pad. A seed layer is formed over the TiW layer, and portions of the seed layer are selectively removed such that remaining seed layer material corresponds to a desired location of interconnect metallurgy for the I/O pad. At least one metal layer is electroplated over the remaining seed layer material, using the TiW layer as a conductive electroplating medium.Type: ApplicationFiled: November 18, 2003Publication date: May 19, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tien-Jen Cheng, David Eichstadt, Jonathan Griffith, Sarah Knickerbocker, Rosemary Previti-Kelly, Roger Quon, Kamalesh Srivastava, Keith Wong
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Publication number: 20050104208Abstract: Disclosed is an improved integrated circuit structure that has internal circuitry and interconnects (e.g. C4, etc.) on an external portion of the structure. With the invention, these interconnects have a metal layer on the external portion of the structure, a first copper layer on the metal layer, a barrier layer on the copper layer, a stabilizing copper layer on the barrier layer, and a tin-based solder bump on the barrier layer. The stabilizing copper layer has a sufficient amount of copper to balance the chemical potential gradient of copper across the barrier layer and prevent copper within the first copper layer from diffusing across the barrier layer. Alternatively, a sufficient amount of copper can be included within the tin-based solder bump to prevent copper from diffusing across the barrier layer. Thus, the tin-based solder bump comprises a copper rich solder alloy.Type: ApplicationFiled: November 14, 2003Publication date: May 19, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Bartelo, Tien-Jen Cheng, David Eichstadt, Charles Goldsmith, Jonathan Griffith, Donald Henderson, Roger Quon, Stephen Kilpatrick
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Publication number: 20050062170Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.Type: ApplicationFiled: September 18, 2003Publication date: March 24, 2005Applicant: International Business Machines CorporationInventors: Julie Biggs, Tien-Jen Cheng, David Eichstadt, Lisa Fanti, Jonathan Griffith, Randolph Knarr, Sarah Knickerbocker, Kevin Petrarca, Roger Quon, Wolfgang Sauter, Kamalesh Srivastava, Richard Volant
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Publication number: 20050026416Abstract: A solder bump for bonding an electronic device to a substrate or another structure is formed by plating a high aspect ratio copper pin on a supporting structure, encapsulating the pin in a barrier material, plating a solder on the barrier material and then reflowing the solder.Type: ApplicationFiled: July 31, 2003Publication date: February 3, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tien-Jen Cheng, David Eichstadt, Jonathan Griffith, Randolph Knarr, Kevin Petrarca, Roger Quon