Patents by Inventor Rohit Kapur

Rohit Kapur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10445225
    Abstract: A method and apparatus of a novel command coverage analyzer is disclosed. Combinations of commands, options, arguments, and values of a product are extracted, customer environment and uses are considered, and a more comprehensive and accurate quality of software process and metric is provided.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: October 15, 2019
    Assignee: Synopsys, Inc.
    Inventors: Chandramouli Gopalakrishnan, Subramanian Chebiyam, Neeraj Surana, Santosh Kulkarni, Rohit Kapur
  • Patent number: 10254343
    Abstract: Methods and apparatuses to generate test patterns for detecting faults in an integrated circuit (IC) are described. During operation, the system receives a netlist and a layout for the IC. The system then generates a set of faults associated with the netlist to model a set of defects associated with the IC. Next, the system determines a set of likelihoods of occurrence for the set of faults based at least on a portion of the layout associated with each fault in the set of faults. The system subsequently generates a set of test patterns to target the set of faults, wherein the set of test patterns are generated based at least on the set of likelihoods of occurrence associated with the set of faults.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: April 9, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Alodeep Sanyal, Girish A. Patankar, Rohit Kapur, Salvatore Talluto
  • Patent number: 10203370
    Abstract: A method for masking scan chains in a test circuit of an integrated circuit is disclosed. A test pattern to be fed into the test circuit of the integrated circuit is generated. The generated test pattern can be used for detecting a primary fault, one or more secondary faults, and one or more tertiary faults. A mask to mask the output of the scan chains of the test circuit is generated. If a condition is not met, a mask that increases the total number of detectable faults is generated. If the condition is met, a mask that protects the primary fault of the test pattern is generated.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: February 12, 2019
    Assignee: Synopsys, Inc.
    Inventors: Jyotirmoy Saikia, Rohit Kapur
  • Publication number: 20180267098
    Abstract: Information is received describing test response signals generated by scan cells of an integrated circuit and physical shift failures representing mismatches between the test response signals and expected test response signals of the integrated circuit. The test response signals are mapped to a subset of the scan cells associated with the physical shift failures. Fault simulation is performed for the mapped subset of the scan cells to identify physical faults located within the integrated circuit causing the physical shift failures.
    Type: Application
    Filed: October 27, 2017
    Publication date: September 20, 2018
    Inventors: Subhadip Kundu, Parthajit Bhattacharya, Rohit Kapur
  • Patent number: 10067187
    Abstract: A method for masking scan chains in a test circuit of an integrated circuit is disclosed. The test circuit includes multiple mask banks. Different mask patterns are stored in each of the mask banks. A first mask bank of the multiple mask banks is selected and the mask pattern stored in the selected first mask bank is used for masking the output of the scan chains of the test circuit during a first portion of a test cycle. A second mask bank of the multiple mask banks is selected and the ask pattern stored in the selected second mask bank is used for masking the output of the scan chains of the test circuit during a second portion of the test cycle.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: September 4, 2018
    Assignee: Synopsys, Inc.
    Inventors: Anshuman Chandra, Subramanian Chebiyam, Jyotirmoy Saikia, Parthajit Bhattacharya, Rohit Kapur
  • Publication number: 20180107587
    Abstract: A method and apparatus of a novel command coverage analyzer is disclosed. Combinations of commands, options, arguments, and values of a product are extracted, customer environment and uses are considered, and a more comprehensive and accurate quality of software process and metric is provided.
    Type: Application
    Filed: May 17, 2016
    Publication date: April 19, 2018
    Inventors: Chandramouli Gopalakrishnan, Subramanian Chebiyam, Neeraj Surana, Santosh Kulkarni, Rohit Kapur
  • Publication number: 20170131354
    Abstract: A method for masking scan chains in a test circuit of an integrated circuit is disclosed. A test pattern to be fed into the test circuit of the integrated circuit is generated. The generated test pattern can be used for detecting a primary fault, one or more secondary faults, and one or more tertiary faults. A mask to mask the output of the scan chains of the test circuit is generated. If a condition is not met, a mask that increases the total number of detectable faults is generated. If the condition is met, a mask that protects the primary fault of the test pattern is generated.
    Type: Application
    Filed: January 24, 2017
    Publication date: May 11, 2017
    Inventors: Jyotirmoy Saikia, Rohit Kapur
  • Publication number: 20170116364
    Abstract: An automated visualization tool in a command line environment allows complex log data to be represented by symbols and associated information for clarity of communication and better understanding of the associated design.
    Type: Application
    Filed: October 26, 2016
    Publication date: April 27, 2017
    Inventors: Anshuman Chandra, Subramanian Chebiyam, Rohit Kapur
  • Patent number: 9588179
    Abstract: A method for masking scan chains in a test circuit of an integrated circuit is disclosed. A test pattern to be fed into the test circuit of the integrated circuit is generated. The generated test pattern can be used for detecting a primary fault, one or more secondary faults, and one or more tertiary faults. A mask to mask the output of the scan chains of the test circuit is generated. If a condition is not met, a mask that increases the total number of detectable faults is generated. If the condition is met, a mask that protects the primary fault of the test pattern is generated.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: March 7, 2017
    Assignee: Synopsys, Inc.
    Inventors: Jyotirmoy Saikia, Rohit Kapur
  • Publication number: 20170059651
    Abstract: A disclosed configuration is for identifying at least one failure indicating scan test cell of a circuit-under-test, CUT, the CUT having a plurality of scan test cells, is provided. The configuration comprises generating a plurality of error signatures by means of a compactor of the CUT, wherein each of the error signatures of the plurality of error signatures consist of a respective sequence of bits comprising at least one failure indicating bit, assigning each error signature to at least a first, a second and a third signature type according to a total number of failure indicating bits of the respective error signature and mapping at least a predefined minimum number of error signatures to respective scan test cells of the plurality of scan test cells. For each error signature, a priority of the mapping is determined by the signature type the respective error signature has been assigned to.
    Type: Application
    Filed: August 25, 2015
    Publication date: March 2, 2017
    Inventors: Subhadip Kundu, Parthajit Bhattacharya, Rohit Kapur
  • Patent number: 9568550
    Abstract: A disclosed configuration is for identifying at least one failure indicating scan test cell of a circuit-under-test, CUT, the CUT having a plurality of scan test cells, is provided. The configuration comprises generating a plurality of error signatures by means of a compactor of the CUT, wherein each of the error signatures of the plurality of error signatures consist of a respective sequence of bits comprising at least one failure indicating bit, assigning each error signature to at least a first, a second and a third signature type according to a total number of failure indicating bits of the respective error signature and mapping at least a predefined minimum number of error signatures to respective scan test cells of the plurality of scan test cells. For each error signature, a priority of the mapping is determined by the signature type the respective error signature has been assigned to.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: February 14, 2017
    Assignee: Synopsys, Inc.
    Inventors: Subhadip Kundu, Parthajit Bhattacharya, Rohit Kapur
  • Publication number: 20160341795
    Abstract: Operating a scan chain of a test circuit of an integrated circuit to have either a single fanout or multiple fanout to a compressor. The test circuit receives a fanout control signal for configuring the fanout of the scan chain. If the fanout control signal indicates configuring of the scan chain with a single fanout, the output of the scan chain is sent to one input of a compressor. If the fanout control signal indicates configuring of the scan chain with multiple fanout, the output of the scan chain is sent to multiple inputs of the compressor.
    Type: Application
    Filed: August 8, 2016
    Publication date: November 24, 2016
    Inventors: Anshuman Chandra, Subramanian B. Chebiyam, Jyotirmoy Saikia, Parthajit Bhattacharya, Rohit Kapur
  • Patent number: 9417287
    Abstract: Operating a scan chain of a test circuit of an integrated circuit to have either a single fanout or multiple fanout to a compressor. The test circuit receives a fanout control signal for configuring the fanout of the scan chain. If the fanout control signal indicates configuring of the scan chain with a single fanout, the output of the scan chain is sent to one input of a compressor. If the fanout control signal indicates configuring of the scan chain with multiple fanout, the output of the scan chain is sent to multiple inputs of the compressor.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: August 16, 2016
    Assignee: Synopsys, Inc.
    Inventors: Anshuman Chandra, Subramanian B. Chebiyam, Jyotirmoy Saikia, Parthajit Bhattacharya, Rohit Kapur
  • Patent number: 9411014
    Abstract: A method for reordering a test pattern set for testing an integrated circuit is disclosed. A productivity index is computed for each test pattern in a test pattern set. The productivity index of a first test pattern and the productivity index of a second test pattern are compared. If the productivity index of the second test pattern is larger than the productivity index of the first test pattern, the location of the first test pattern and the second test pattern are swapped.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: August 9, 2016
    Assignee: Synopsys, Inc.
    Inventors: Sushovan Podder, Parthajit Bhattacharya, Rohit Kapur
  • Patent number: 9342439
    Abstract: A method and apparatus of a novel command coverage analyzer is disclosed. Combinations of commands, options, arguments, and values of a product are extracted, customer environment and uses are considered, and a more comprehensive and accurate quality of software process and metric is provided.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: May 17, 2016
    Assignee: Synopsys, Inc.
    Inventors: Chandramouli Gopalakrishnan, Subramanian Chebiyam, Neeraj Surana, Santosh Kulkarni, Rohit Kapur
  • Patent number: 9329235
    Abstract: A method for localizing at least one scan flop associated with a fault in an integrated circuit. A first test pattern, including a first scan-in data and first control data, is generated. Based on the first control data of the first test pattern, a first fault data is generated by applying the first scan-in data of the first test pattern to scan flops in a test circuit of the integrated circuit. If the first fault data indicates that a fault may be present in the integrated circuit, a second test pattern, including a second scan-in data and a second control data is generated.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: May 3, 2016
    Assignee: Synopsys, Inc.
    Inventors: Parthajit Bhattacharya, Rohit Kapur
  • Patent number: 9239897
    Abstract: A core circuit that can be connected in a hierarchical manner, and configured to test a multiple circuits is disclosed. The core circuit includes at least one real input for receiving scan-in data for controlling operation of the core circuit. The core circuit further includes an input register coupled to the at least one real input and configured to store data. The core circuit further includes at least one scan chain coupled a subset if registers of the register chain and configured to generate scan-out data representing the presence of faults in an circuit. Furthermore, the core circuit includes at least one control pseudo-output coupled to the input register and configured to route at least a subset of the data to another register chain in the core circuit or to another core circuit.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: January 19, 2016
    Assignee: Synopsys, Inc.
    Inventors: Subramanian B. Chebiyam, Santosh Kulkarni, Anshuman Chandra, Rohit Kapur
  • Publication number: 20150363295
    Abstract: A method and apparatus of a novel command coverage analyzer is disclosed. Combinations of commands, options, arguments, and values of a product are extracted, customer environment and uses are considered, and a more comprehensive and accurate quality of software process and metric is provided.
    Type: Application
    Filed: June 11, 2015
    Publication date: December 17, 2015
    Inventors: Chandramouli Gopalakrishnan, Subramanian Chebiyam, Neeraj Surana, Santosh Kulkarni, Rohit Kapur
  • Patent number: 8954918
    Abstract: Roughly described, a scan-based test architecture is optimized in dependence upon the circuit design under consideration. In one embodiment, a plurality of candidate test designs are developed. For each, a plurality of test vectors are generated in dependence upon the circuit design and the candidate test design, preferably using the same ATPG algorithm that will be used downstream to generate the final test vectors for the production integrated circuit device. A test protocol quality measure such as fault coverage is determined for each of the candidate test designs, and one of the candidate test designs is selected for implementation in an integrated circuit device in dependence upon a comparison of such test protocol quality measures. Preferably, only a sampling of the full set of test vectors that ATPG could generate, is used to determine the number of potential faults that would be found by each particular candidate test design.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: February 10, 2015
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Jyotirmoy Saikia, Rajesh Uppuluri, Pramod Notiyath, Tammy Fernandes, Santosh Kulkarni, Ashok Anbalan
  • Publication number: 20150025819
    Abstract: A method for masking scan chains in a test circuit of an integrated circuit is disclosed. The test circuit includes multiple mask banks. Different mask patterns are stored in each of the mask banks. A first mask bank of the multiple mask banks is selected and the mask pattern stored in the selected first mask bank is used for masking the output of the scan chains of the test circuit during a first portion of a test cycle. A second mask bank of the multiple mask banks is selected and the ask pattern stored in the selected second mask bank is used for masking the output of the scan chains of the test circuit during a second portion of the test cycle.
    Type: Application
    Filed: July 18, 2014
    Publication date: January 22, 2015
    Inventors: Anshuman Chandra, Subramanian Chebiyam, Jyotirmoy Saikia, Parthajit Bhattacharya, Rohit Kapur