Abstract: A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault.

Abstract: A filter for preventing uncertain bits output by test scan chains from being provided to a MISR is provided. The filter can include a gating structure for receiving a bit from a scan chain and control circuitry for providing a predetermined signal to the gating structure if the bit is an uncertain bit. In one embodiment, the gating structure can include a logic gate, such as an AND or an OR gate. The control circuitry can include components substantially similar to the pattern generator providing signals to the scan chain. For example, the control circuitry can include an LFSR and a PRPG shadow for loading the LFSR. In one embodiment, the control circuitry can further include a phase-shifter for receiving inputs from the LFSR and providing outputs to the gating structure.

Abstract: A system for automatically retargeting test vectors for application on tester systems having different performance capabilities is provided. The system includes a user selectable mode selector that can be adjustable between different performance modes, e.g. high, medium, and low. In high performance mode, the system allows test vectors to be applied using a high performance test system, e.g. a tester having high pin count. In low performance mode, the same test vectors can be applied but using a low performance test system, e.g. a tester having low pin count. By allowing the same test vectors to be used in a high performance or a low performance test environment, a testing facility can make maximum use of its available testing equipment for efficiently testing a device.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A system and method for time slicing deterministic patterns for reseeding in logic built-in self-test (BIST). The known properties of a linear feedback shift register (LFSR) and an associated set of channels are used in conjunction with a desired deterministic test pattern to create one or more seeds which can be used by the LFSR to generate the test pattern. The test pattern is divided into a number of segments, with each segment having a specific number of “care” bits. The number of shifts required to fill a segment using a particular seed is stored along with the seed as a seed lifetime. During testing, each deterministic test pattern is generated by loading a seed into the LFSR and cycling the LFSR in accordance with the lifetime of the seed. The seed lifetimes may have different values, and multiple seeds may be used in the generation of a single test pattern, or a single seed may be used to generate care bits of multiple test patterns.

Abstract: A process and system for placement planning for test mode circuitry of an integrated circuit design. The novel method includes the steps of partitioning a scan chain of a netlist into sets of re-orderable scan cells. The netlist is passed to layout processes and therein the scan cells of the scan chain are re-ordered based on the sets. According to one embodiment of the present invention, the scan-chain is partitioned into a number of different sets based the respective clock domains, edge sensitivity types, skew tolerance levels, surrounding cone logic, reconfigurability and simultaneous output switching requirements of the scan cells. Data representative of the resulting sets are then provided to the place-and-route processes to be used as re-ordering limitations. Particularly, the re-ordering limitations restrict the rearrangement of scan cells among different sets. The placement and routing processes, however, are not restricted from rearranging the order of scan cells within the same set.

Abstract: In a computer implemented synthesis system, a method of generating a test pattern for use in testing device with ATE (automated test equipment). The computer implemented steps of receiving a netlist specification representing a design to be realized in physical form and storing the netlist specification in a computer memory unit, and simulating the netlist using the computer implemented synthesis system. Using the simulation instantiated within the synthesis system, deterministic test pattern generation is performed to obtain a first portion (partial) of a test pattern. The test pattern is operable to detect a fault in the circuit netlist once speculative test pattern generation is performed to obtain a remaining portion of the test pattern. The first portion and the remaining portion of the test pattern comprise a test vector operable to detect the fault when used with automated test equipment for testing a device resulting from the design.

Abstract: According to the present invention, during scan conversion, non-scan memory cells of a circuit design are replaced with scan cells to form a scan chain. The scan chain is transformed by the test synthesis tool of the present invention into dynamic scan chains with the addition of reconfiguration circuitry. The reconfiguration circuitry partitions the scan chain into multiple segments and enables each segment to be selectively “bypassed” (or deactivated) during test application. Shorter test patterns that are only pertinent to one or more segments are necessary, resulting in a reduction in overall test data volume and test application time. The present invention also provides a modified ATPG technique for generating test patterns for the dynamic scan chains.

Abstract: A method for generating a test pattern for use in testing an integrated circuit device. The computer implemented steps of receiving and storing the netlist specification in a computer memory unit, and simulating the netlist using the computer implemented synthesis system. Using the netlist simulation, a set of circuit paths for each fault of the plurality of faults within the netlist specification is determined. From this set of paths, respective longest paths for each fault is determined. Using an ATPG (automatic test pattern generation) process, a test vector is determined for the first fault. Transition fault simulation is then performed on the first fault by applying the test vector to a first path through the first fault, wherein the first path is the longest path traversing through the first fault as determined by the ATPG process.

Abstract: A process and system for placement planning for test mode circuitry of an integrated circuit design. The novel method includes the steps of partitioning a scan chain of a netlist into sets of re-orderable scan cells. The netlist is passed to layout processes and therein the scan cells of the scan chain are re-ordered based on the sets. According to one embodiment of the present invention, the scan-chain is partitioned into a number of different sets based the respective clock domains, edge sensitivity types skew tolerance levels, surrounding cone logic, reconfigurability and simultaneous output switching requirements of the scan cells. Data representative of the resulting sets are then provided to the place-and-route processes to be used as re-ordering limitations. Particularly, the re-ordering limitations restrict the rearrangement of scan cells among different sets. The placement and routing processes, however, are not restricted from rearranging the order of scan cells within the same set.

Abstract: A method and circuit for testing an integrated circuit device using intelligent test vector formatting that reduces the storage required for test patterns and also provides encryption of the test patterns. A first memory stores a test vector mask that is a sequence of bits to indicate if corresponding test vector data is deterministic or random. The test vector data contains a portion that is deterministically generated by automatic test pattern generation (ATPG) software and a portion that is random. A second memory contains a sequence of bits that represent the deterministic test vector data. A random number generator (e.g., linear feed-back shift register, LFSR) generates a reproducible sequence of pseudo random bits that is based on a seed value. A selector circuit is used to select bits either from the second memory or from the random number generator based on the value of the mask vector. The output of the selector provides a fully specified test vector for application to the device under test (DUT).

Abstract: A computer implemented method of constructing a scan chain. According to the present invention, scan cells are inserted into a netlist description of an integrated circuit design and are coupled serially together to form a scan chain. The resulting netlist is then passed to layout processes where the cells of the integrated circuit design are automatically placed and routed. The layout processes are performed without regard to any predetermined constraints designating any particular functional pins of the netlist design as scan-in or scan-out ports for the scan chain. After the cells are placed, a first functional pin is selected as the scan-in port and a second functional pin is selected as the scan-out port according to cell placement information. In particular, the functional pin that is closest to the leading scan cell is selected as the scan-in port. The functional pin that is closest to the last scan cell is selected as the scan-out port for the scan chain.

Abstract: A method and system for improving the fault coverage of test vectors for testing integrated circuits. The present invention also provides a method and system for reducing the number of deterministic test vectors required for testing integrated circuits by inserting test points in a cost effective manner. According to an embodiment of the present invention, a fault list having all the potential faults of an integrated circuit design is initialized and all the potential faults are marked as untestable. A set of test patterns, T, for testing several of the potential faults are generated. A fault simulation process is then performed on the integrated circuit design with the test patterns, T, to mark off untested faults. During fault simulation, fault propagation is monitored to determine the nets in the design to which faults were propagated. The nets at which fault propagation discontinues (e.g., de-sensitized) are also monitored. This information is collected over the set of test patterns, T.

Abstract: An efficient method of selecting flip-flops to be made scannable in a digital integrated circuit design for purposes of improving testability without incurring the overhead of full-scan, comprising the steps of (a) partitioning the faults in the circuit into a first fault type and a second fault type, (b) selecting a static characterization algorithm for characterizing the first and second fault types, (c) determining the relationship between attainable fault coverage and the characterized values for the first and second fault types, (d) characterizing the first and second fault types for each candidate flip-flop for scan in the digital integrated circuit with the static characterization algorithm, (e) determining the first and second fault types that are the closest together in value, (f) selecting the flip-flop associated with the first and second fault types determined in step (e), (g) forming a shift register with flip-flop selected in step (f), (h) repeating steps (d)-(g) until the attainable fault cover