Abstract: A magneto resistive memory contains first switches, a word line voltage source generating a word line voltage connected to the first switches, a line node, second switches, and cells formed of cell resistors each having a first terminal connected to the word line voltage through one of the first switches and a second terminal connected to the line node through one of the second switches. A reference resistor is connected to the line node and a reference voltage source is connected to the reference resistor. The reference resistor with the reference voltage source brings about a reduction in a respective cell current, flowing from the line node, by an average current. A device is connected to the line node and evaluates the cell resistors. The device has an amplifier for converting a difference between the respective cell current and the average current into a voltage functioning as an evaluation signal.

Abstract: The circuit configuration and the associated method allow reducing the 1/f noise of MOSFETs in an electronic circuit, especially in an integrated circuit with one or more MOSFETs. At least one direct current and/or at least one direct voltage source for adjusting constant working point(s) of the MOSFET(s) is/are assigned to one or more or all MOSFETs. At least one periodically oscillating current and/or voltage source is assigned to one or more or all MOSFETs so that the respective working points periodically oscillate about the constant working point(s) in such a manner that impurity states in the oxide of the MOSFET, which are recharged under the condition of a constant working point according to the principles of statistics such that they determine the 1/f noise signal, are no longer recharged statistically but at a lower probability due to the modulatory frequency of the periodically oscillating sources.

Abstract: A magnetoresistive memory is described and contains a common word line voltage source, bit lines, word lines crossing the bit lines, and a memory cell array having memory cells with cell resistors. The memory cell array further has reference cells with reference cell resistors. The memory cell array is configured such that for testing a respective cell resistor in each case two of the reference cell resistors nearest the respective cell resistor and the reference cell are simultaneously connected to a common word line voltage. A first feedback amplifier together with the two reference cell resistors form a summing amplifier. A second feedback amplifier together with the respective cell resistor form an amplifier having an equivalent gain as the summing amplifier. A comparator is connected to the summing amplifier and the amplifier. The comparator has an output supplying an evaluation signal dependent on the respective cell resistor.

Abstract: A magnetoresistive memory includes magnetoresistive memory cells disposed in a plurality of rows and/or columns. A bit line is connected to first poles of the memory cells of a column. A word line is connected to second poles of the memory cells of a row. A read voltage source is separately connectable to first ends of the word lines. A voltage evaluator has at least one input that is separately connectable to first ends of the bit lines via an evaluation line. A first terminating resistor branches from the evaluation line. An impedance converter has an input connected to the evaluation line and has an output separately connectable to second ends of the bit lines and word lines. The invention also relates to a method of reading magnetoresistive memories.

Abstract: A resistor cascade has a multiplicity of electrical resistors connected in series, and each electrical resistor has at least one single-walled carbon nanotube.

Abstract: The integrated memory has memory cells with a magnetoresistive storage effect in a memory cell array in the form of a matrix. The memory cells are each connected between one of the column lines and one of the row lines. The column lines are each connected to a read amplifier for reading a data signal from a memory cell. The read amplifier has an operational amplifier with feedback, and a first control input connected to one of the column lines. A capacitor is connected between a second control input of the operational amplifier and a terminal for a supply potential and is used to compensate for any offset voltage at the control inputs of the operational amplifier. This allows a data signal which is to be read from one of the memory cells to be detected comparatively reliably.

Abstract: A description is given of a method and a circuit configuration for evaluating an information content of a memory cell, preferably of an MRAM memory cell, or of a memory cell array. In order to be able to perform accurate and reliable evaluation of the memory cell, a first current value flowing through the memory cell or a voltage value correlated with the current value is measured and conducted through a first circuit branch, which has a switch and a capacitance, and is buffer-stored. The memory cell is subsequently subjected to a programming operation. Afterward, in the same memory cell a second current value or voltage value is measured and conducted through a second circuit branch that has a switch and a capacitance and is buffer-stored there. The two measured values are compared with one another in an evaluation unit.

Abstract: A resistor cascade has a multiplicity of electrical resistors connected in series, and each electrical resistor has at least one single-walled carbon nanotube.

Abstract: A magneto resistive memory contains first switches, a word line voltage source generating a word line voltage connected to the first switches, a line node, second switches, and cells formed of cell resistors each having a first terminal connected to the word line voltage through one of the first switches and a second terminal connected to the line node through one of the second switches. A reference resistor is connected to the line node and a reference voltage source is connected to the reference resistor. The reference resistor with the reference voltage source brings about a reduction in a respective cell current, flowing from the line node, by an average current. A device is connected to the line node and evaluates the cell resistors. The device has an amplifier for converting a difference between the respective cell current and the average current into a voltage functioning as an evaluation signal.

Abstract: A magnetoresistive memory is described and contains a common word line voltage source, bit lines, word lines crossing the bit lines, and a memory cell array having memory cells with cell resistors. The memory cell array further has reference cells with reference cell resistors. The memory cell array is configured such that for testing a respective cell resistor in each case two of the reference cell resistors nearest the respective cell resistor and the reference cell are simultaneously connected to a common word line voltage. A first feedback amplifier together with the two reference cell resistors form a summing amplifier. A second feedback amplifier together with the respective cell resistor form an amplifier having an equivalent gain as the summing amplifier. A comparator is connected to the summing amplifier and the amplifier. The comparator has an output supplying an evaluation signal dependent on the respective cell resistor.

Abstract: A magnetoresistive memory includes magnetoresistive memory cells disposed in a plurality of rows and/or columns. A bit line is connected to first poles of the memory cells of a column. A word line is connected to second poles of the memory cells of a row. A read voltage source is separately connectable to first ends of the word lines. A voltage evaluator has at least one input that is separately connectable to first ends of the bit lines via an evaluation line. A first terminating resistor branches from the evaluation line. An impedance converter has an input connected to the evaluation line and has an output separately connectable to second ends of the bit lines and word lines. The invention also relates to a method of reading magnetoresistive memories.

Abstract: A clock configuration for driving switched op-amp circuits operated in opposite phases is presented in which a common off-phase of variable length is inserted between the on-phases of the individual operational amplifiers. The length of the off-phase can be adapted to the transient response of the operational amplifiers used. The clock configuration according to the invention can be used for further reducing the power consumption of switched op-amp circuits.

Abstract: The magnetoresistive memory provides for an improvement in interference immunity even though only a small chip area is used. Word lines are situated vertically between two complementary bit lines, a magnetoresistive memory system of a regular location is situated between a bit line and a word line, and an appertaining magnetoresistive layer system of a complementary memory location is situated between the complementary bit line and the word line in the vertical direction.

Abstract: The magnetoresistive memory provides for an improvement in interference immunity even though only a small chip area is used. Word lines are situated vertically between two complementary bit lines, a magnetoresistive memory system of a regular location is situated between a bit line and a word line, and an appertaining magnetoresistive layer system of a complementary memory location is situated between the complementary bit line and the word line in the vertical direction.

Abstract: The magnetoresistive memory has a reduced current density in the bit lines and/or word lines. This avoids electromigration problems. The current density is reduced such that a compact field concentration is attained, for example, by the use of ferrite in the area around the magnetic memory cells.

Abstract: The integrated memory has memory cells with a magnetoresistive storage effect in a memory cell array in the form of a matrix. The memory cells are each connected between one of the column lines and one of the row lines. The column lines are each connected to a read amplifier for reading a data signal from a memory cell. The read amplifier has an operational amplifier with feedback, and a first control input connected to one of the column lines. A capacitor is connected between a second control input of the operational amplifier and a terminal for a supply potential and is used to compensate for any offset voltage at the control inputs of the operational amplifier. This allows a data signal which is to be read from one of the memory cells to be detected comparatively reliably.

Abstract: A circuit with a delay stage formed by an invertor having high-impedance transistors and, connected in series therewith, an invertor having low-impedance transistors MOS capacitors are provided between the gates of the transistors of the low-impedance invertor and the output of the delay stage. By means of this circuit, delay stages with steep edges can be realized with comparatively less outlay on components.

Abstract: The circuit arrangement has two electrical quantities in the form of a first quadrature-axis current component (I.sub.1) and of a second quadrature-axis current component (I.sub.2) that are compared to one another. The circuit arrangement has a first inverter unit (n.sub.1, p.sub.1) and a second inverter unit (n.sub.2, p.sub.2). Respectively one output (50, 52) of the two inverter units ((n.sub.1, p.sub.1, (n.sub.2, p.sub.2)) are coupled to an input of the respectively other inverter unit (52, 53). A reset unit (5) that initiates the comparison of the currents when activated is located between the two outputs of the two inverter units (n.sub.1, p.sub.2). When the reset unit (5) is deactivated, the output datum obtained in the evaluation remains stable.

Abstract: An associative memory contains cells that are formed of a series circuit of an ordinary PMOS transistor with a PMOS transistor with a floating gate. The ordinary PMOS transistor receives of an input vector and the gate of the second PMOS transistor is connected to a learning input. For the associative access, a second vector can be applied to the drain terminal of the second PMOS transistor and, upon readout, the current flow through the respective series circuit is evaluated column-by-column by current evaluator circuits.

Abstract: A digital memory matrix having memory cells in rows and columns, addressing of the memory cells is accomplished by control devices which perform arbitrary jumps of address, thereby avoiding addressing on adjacent lines. The jump increment is selectable. The control devices are control chains, two of which are provided, and the outputs of the control chains are connected to linking elements that in turn are connected to the memory lines. The linking elements are provided in groups.