Patents by Inventor Romain Ygnace

Romain Ygnace has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11366198
    Abstract: A method for processing a radar signal includes adjusting a processing clock signal, wherein the processing clock signal determines an operation period of a signal processing circuit, wherein the processing clock signal is determined based on a time window, wherein the size of the time window is determined based on the maximum time available for processing a portion of the radar signal and wherein the end of the time window is determined such that it does not occur during an active transmission portion of the radar system.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: June 21, 2022
    Assignee: Infineon Technologies AG
    Inventors: Markus Bichl, Ljudmil Anastasov, Romain Ygnace
  • Publication number: 20220103218
    Abstract: A method of handling radar signals of a radar system having a plurality of antennas is provided. The method includes processing a plurality of radar signals for determining a distance between the radar system and at least one target and a velocity of the at least one target, thereby forming a plurality of processed radar signals. Each radar signal of the plurality of radar signals is received by an associated antenna of the plurality of antennas. The plurality of processed radar signals are digitally beamformed for at least one beam direction, thereby forming a plurality of beamformed radar signals. The plurality of beamformed radar signals are summed from the plurality of antennas per beam direction.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 31, 2022
    Inventors: Andre Roger, Markus Bichl, Farhan Bin Khalid, Dian Tresna Nugraha, Romain Ygnace
  • Patent number: 11232034
    Abstract: A cache circuit associated with a hypervisor system is disclosed. The cache circuit comprises a cache memory circuit comprising a plurality of cachelines, wherein each cacheline is configured to store data associated with one or more virtual machines (VMs) of a plurality of VMs associated with the hypervisor system and a plurality of tag array entries respectively associated with the plurality of cachelines. In some embodiments, each tag array entry of the plurality of tag entries comprises a tag field configured to store a tag identifier (ID) that identifies an address of a main memory circuit to which a data stored in the corresponding cacheline is associated and a VM tag field configured to store a VM ID associated with a VM to which the data stored in the corresponding cacheline is associated.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: January 25, 2022
    Assignee: Infineon Technologies AG
    Inventors: Manoj Kumar Harihar, Romain Ygnace
  • Publication number: 20210263706
    Abstract: A radar device is configured to: select a set of operands comprising several operands, determine a common exponent for the operands of the set of operands, normalize the operands based on the common exponent, compress each operand by reducing the resolution of its mantissa, and store the common exponent and the compressed operands in a memory. Also, a vehicle including such radar device and an according method as well as computer program product are provided.
    Type: Application
    Filed: February 19, 2021
    Publication date: August 26, 2021
    Inventors: Andre Roger, Markus Bichl, Dian Tresna Nugraha, Romain Ygnace
  • Patent number: 11099256
    Abstract: A device for processing radar signals is suggested, the device comprising: (i) a memory, which is arranged to store radar data and (ii) an accessor comprising a DMA engine, wherein the accessor is arranged to access data of the memory via the DMA engine, to filter the accessed data, and to forward the filtered data.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: August 24, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andre Roger, Christian Schmid, Romain Ygnace
  • Publication number: 20210255278
    Abstract: A radar sensor is described herein. In accordance with one example embodiment the radar sensor includes a transmitter for transmitting an RF signal and a receiver configured to receive a respective back-scattered signal from at least one radar target and to provide a corresponding digital radar signal. The radar sensor further includes a processor configured to convert the digital radar signal into the frequency do-main thus providing respective frequency domain data and to compress the frequency domain data. A communication interface is configured to transmit the compressed frequency domain data via a communication link operably coupled to the communication interface. Furthermore, respective and related radar methods and systems are described.
    Type: Application
    Filed: April 30, 2021
    Publication date: August 19, 2021
    Inventors: Andre ROGER, Markus BICHL, Dian Tresna NUGRAHA, Romain YGNACE
  • Publication number: 20210258021
    Abstract: A processor having a hardware decompressor configured to pad a non-equidistant data set, which is data received at irregular time intervals, with one or more of a predefined value, wherein the data is radar or optical sensor data; and a Fourier transform engine configured to receive the padded non-equidistant data set directly and continuously per data set from the hardware decompressor, and to FFT process the received padded non-equidistant data set.
    Type: Application
    Filed: February 18, 2020
    Publication date: August 19, 2021
    Inventors: Andre Roger, Markus Bichl, Romain Ygnace
  • Patent number: 11085994
    Abstract: A radar device including at least three subcircuits, wherein each subcircuit has a cascade input port and a cascade output port and is chained such that the cascade output port of a first subcircuit is connected to the cascade input port of a subsequent subcircuit, the cascade input port of the last subcircuit of the chain is connected to the cascade output port of its preceding subcircuit, and the cascade output port of the last subcircuit of the chain is connectable to an external device, and wherein the at least three subcircuits are configured to conduct a radar computation in a distributed manner such that intermediate results are conveyed towards the last subcircuit of the chain which is configured to combine these results and supply them towards its cascade output port.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: August 10, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andre Roger, Romain Ygnace
  • Publication number: 20210141055
    Abstract: A radar device is provided comprising a first processing unit, a radar circuitry, at least one security circuitry, at least one secure memory, and a secure interface arranged for communicating with a second processing unit that is external to the radar device, wherein the first processing unit is arranged to configure and/or run the radar device based on parameters obtained via the secure interface from the second processing unit.
    Type: Application
    Filed: November 9, 2020
    Publication date: May 13, 2021
    Inventors: Andre ROGER, Romain YGNACE
  • Patent number: 10996311
    Abstract: A radar sensor is described herein. In accordance with one example embodiment the radar sensor includes a transmitter for transmitting an RF signal and a receiver configured to receive a respective back-scattered signal from at least one radar target and to provide a corresponding digital radar signal. The radar sensor further includes a processor configured to convert the digital radar signal into the frequency do-main thus providing respective frequency domain data and to compress the frequency domain data. A communication interface is configured to transmit the compressed frequency domain data via a communication link operably coupled to the communication interface. Furthermore, respective and related radar methods and systems are described.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: May 4, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andre Roger, Markus Bichl, Dian Tresna Nugraha, Romain Ygnace
  • Publication number: 20210116535
    Abstract: A method of handling radar signals of a radar system having a plurality of antennas is provided. The method may include generating a plurality of time-based radar signals based on a radar signal received by an associated antenna of the plurality of antennas, and transforming each time-based radar signal of the time-based radar signals into radar signals that each comprise a plurality of pairs of a frequency-based-value and an associated intensity value.
    Type: Application
    Filed: September 30, 2020
    Publication date: April 22, 2021
    Inventors: Andre Roger, Markus Bichl, Dian Tresna Nugraha, Romain Ygnace
  • Publication number: 20210116533
    Abstract: A radar device is provided that is arranged for conducting an interference detection and mitigation based on received and sampled radar signals and storing interference-mitigated data; conducting an FFT on the interference-mitigated data and storing FF-transformed data; conducting a compression on the FF-transformed data into compressed data; and storing the compressed data in a memory. Also, a method for operating such radar device is suggested.
    Type: Application
    Filed: October 16, 2020
    Publication date: April 22, 2021
    Inventors: Andre Roger, Markus Bichl, Farhan Bin Khalid, Romain Ygnace
  • Publication number: 20210096899
    Abstract: A cache circuit associated with a hypervisor system is disclosed. The cache circuit comprises a cache memory circuit comprising a plurality of cachelines, wherein each cacheline is configured to store data associated with one or more virtual machines (VMs) of a plurality of VMs associated with the hypervisor system and a plurality of tag array entries respectively associated with the plurality of cachelines. In some embodiments, each tag array entry of the plurality of tag entries comprises a tag field configured to store a tag identifier (ID) that identifies an address of a main memory circuit to which a data stored in the corresponding cacheline is associated and a VM tag field configured to store a VM ID associated with a VM to which the data stored in the corresponding cacheline is associated.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Inventors: Manoj Kumar Harihar, Romain Ygnace
  • Patent number: 10929949
    Abstract: A device for accessing memory configured to store an image data cube, wherein the memory has memory banks, and each memory bank has memory rows and memory columns. The device includes an input configured to receive a memory access request having a logical start address, which specifies a logical bank, a logical row, and a logical column, and a burst size; and a memory address generator configured to generate physical memory addresses based on the logical start address and the burst size, wherein any consecutive logical start addresses mapped to different memory rows are mapped to different memory banks.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: February 23, 2021
    Assignee: Infineon Technologies AG
    Inventors: Muhammad Hassan, Pedro Costa, Andre Roger, Romain Ygnace
  • Patent number: 10852409
    Abstract: A device for processing radar signals is suggested, said device comprising a DMA engine, a buffer and a processing stage, wherein the DMA engine is arranged for conducting a read access to a memory, wherein such read access comprises at least two data entries, and for filling the buffer by resorting the at least two data entries, wherein the processing stage is arranged for processing the data stored in the buffer.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: December 1, 2020
    Assignee: Infineon Technologies AG
    Inventors: Dian Tresna Nugraha, Andre Roger, Romain Ygnace
  • Publication number: 20200341134
    Abstract: The present disclosure relates to a radar device including a first radar-IC for processing first receive signals from first antennas of an antenna array, wherein the first radar-IC is configured to determine a first range-Doppler map based on the first receive signals, and to determine a first subregion of the first range-Doppler map based on criteria of interest. The radar device also includes at least a second radar-IC for processing second receive signals from second antennas of the antenna array, wherein the second radar-IC is configured to determine a second range-Doppler map based on the second receive signals, and to determine a second subregion of the second range-Doppler map based on the criteria of interest. A data interface is configured to forward information indicative of the first and/or the second subregions to a common processor for further processing.
    Type: Application
    Filed: April 22, 2020
    Publication date: October 29, 2020
    Applicant: Infineon Technologies AG
    Inventors: Andre ROGER, Farhan Bin KHALID, Paul MEISSNER, Dian Tresna NUGRAHA, Romain YGNACE
  • Patent number: 10802134
    Abstract: A method for processing radar signals includes emitting a first radar signal via a transmitting antenna of a first radar unit, where the first radar signal is phase modulated using a first code and a first frequency offset is added to at least a portion of the first radar signal, and emitting a second radar signal via a transmitting antenna of a second radar unit, where the second radar signal is phase modulated using a second code. The first code and the second code are orthogonal to each other and the first radar unit and the second radar unit are loosely coupled with each other. The method further includes receiving a combined radar signal via a receiving antenna of the first radar unit, where the combined radar signal comprises a reflections of the first and the second radar signals, and processing the combined radar signal at the first radar unit.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: October 13, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andre Roger, Herbert Jaeger, Farhan Bin Khalid, Romain Ygnace
  • Patent number: 10796617
    Abstract: An implementation relates to a device for processing an image data stream. The device may include a first processing unit and a second processing unit for receiving the image data stream. The first processing unit may be arranged for providing a first data stream, the first data stream has a reduced bandwidth compared to the image data stream. The second processing unit may arranged for providing a second data stream, the second data stream has a reduced bandwidth compared to the image data stream.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: October 6, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andre' Roger, Romain Ygnace
  • Publication number: 20200311863
    Abstract: A device for accessing memory configured to store an image data cube, wherein the memory has memory banks, and each memory bank has memory rows and memory columns. The device includes an input configured to receive a memory access request having a logical start address, which specifies a logical bank, a logical row, and a logical column, and a burst size; and a memory address generator configured to generate physical memory addresses based on the logical start address and the burst size, wherein any consecutive logical start addresses mapped to different memory rows are mapped to different memory banks.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Muhammad Hassan, Pedro Costa, Andre Roger, Romain Ygnace
  • Publication number: 20200256950
    Abstract: A method for processing a radar signal includes adjusting a processing clock signal, wherein the processing clock signal determines an operation period of a signal processing circuit, wherein the processing clock signal is determined based on a time window, wherein the size of the time window is determined based on the maximum time available for processing a portion of the radar signal and wherein the end of the time window is determined such that it does not occur during an active transmission portion of the radar system.
    Type: Application
    Filed: January 24, 2020
    Publication date: August 13, 2020
    Inventors: Markus Bichl, Ljudmil Anastasov, Romain Ygnace