Patents by Inventor Roman CAUDILLO
Roman CAUDILLO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11355623Abstract: Embodiments of the present disclosure describe a method of fabricating spin qubit device assemblies that utilize dopant-based spin qubits, i.e. spin qubit devices which operate by including a donor or an acceptor dopant atom in a semiconductor host layer. The method includes, first, providing a pair of gate electrodes over a semiconductor host layer, and then providing a window structure between the first and second gate electrodes, the window structure being a continuous solid material extending between the first and second electrodes and covering the semiconductor host layer except for an opening through which a dopant atom is to be implanted in the semiconductor host layer. By using a defined gate-first process, the method may address the scalability challenges and create a deterministic path for fabricating dopant-based spin qubits in desired locations, promoting wafer-scale integration of dopant-based spin qubit devices for use in quantum computing devices.Type: GrantFiled: March 19, 2018Date of Patent: June 7, 2022Assignee: Intel CorporationInventors: Lester Lampert, James S. Clarke, Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Kanwaljit Singh, Roman Caudillo, Hubert C. George, Zachary R. Yoscovits, Nicole K. Thomas
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Patent number: 11335778Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.Type: GrantFiled: June 26, 2018Date of Patent: May 17, 2022Assignee: Intel CorporationInventors: Nicole K. Thomas, Ravi Pillarisetty, Kanwaljit Singh, Hubert C. George, David J. Michalak, Lester Lampert, Zachary R. Yoscovits, Roman Caudillo, Jeanette M. Roberts, James S. Clarke
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Publication number: 20220140069Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: January 19, 2022Publication date: May 5, 2022Inventors: Sudipto NASKAR, Manish CHANDHOK, Abhishek A. SHARMA, Roman CAUDILLO, Scott B. CLENDENNING, Cheyun LIN
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Publication number: 20220140068Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: January 18, 2022Publication date: May 5, 2022Inventors: Sudipto NASKAR, Manish CHANDHOK, Abhishek A. SHARMA, Roman CAUDILLO, Scott B. CLENDENNING, Cheyun LIN
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Patent number: 11264449Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.Type: GrantFiled: March 24, 2020Date of Patent: March 1, 2022Assignee: Intel CorporationInventors: Sudipto Naskar, Manish Chandhok, Abhishek A. Sharma, Roman Caudillo, Scott B. Clendenning, Cheyun Lin
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Publication number: 20220013658Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.Type: ApplicationFiled: September 10, 2021Publication date: January 13, 2022Applicant: Intel CorporationInventors: Ravi Pillarisetty, Van H. Le, Nicole K. Thomas, Hubert C. George, Jeanette M. Roberts, Payam Amin, Zachary R. Yoscovits, Roman Caudillo, James S. Clarke, Roza Kotlyar, Kanwaljit Singh
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Patent number: 11183564Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.Type: GrantFiled: June 21, 2018Date of Patent: November 23, 2021Assignee: Intel CorporationInventors: Nicole K. Thomas, Ravi Pillarisetty, Payam Amin, Roza Kotlyar, Patrick H. Keys, Hubert C. George, Kanwaljit Singh, James S. Clarke, David J. Michalak, Lester Lampert, Zachary R. Yoscovits, Roman Caudillo, Jeanette M. Roberts
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Patent number: 11158731Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.Type: GrantFiled: September 28, 2017Date of Patent: October 26, 2021Assignee: Intel CorporationInventors: Ravi Pillarisetty, Van H. Le, Nicole K. Thomas, Hubert C. George, Jeanette Roberts, Payam Amin, Zachary R. Yoscovits, Roman Caudillo, James S. Clarke, Roza Kotlyar, Kanwaljit Singh
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Publication number: 20210328019Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.Type: ApplicationFiled: July 1, 2021Publication date: October 21, 2021Applicant: Intel CorporationInventors: Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Ravi Pillarisetty, Kanwaljit Singh, Payam Amin, Hubert C. George, Jeanette M. Roberts, Roman Caudillo, David J. Michalak, Zachary R. Yoscovits, Lester Lampert
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Publication number: 20210305358Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 24, 2020Publication date: September 30, 2021Inventors: Sudipto NASKAR, Manish CHANDHOK, Abhishek A. SHARMA, Roman CAUDILLO, Scott B. CLENDENNING, Cheyun LIN
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Patent number: 11114530Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.Type: GrantFiled: December 17, 2017Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Ravi Pillarisetty, Kanwaljit Singh, Payam Amin, Hubert C. George, Jeanette M. Roberts, Roman Caudillo, David J. Michalak, Zachary R. Yoscovits, Lester Lampert
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Patent number: 11107891Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous first rows and the plurality of second gates are arranged in electrically continuous second rows parallel to the first rows. Quantum dot devices according to various embodiments of the present disclosure are based on arranging first and second gates in hexagonal/honeycomb arrays.Type: GrantFiled: December 23, 2017Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: Ravi Pillarisetty, Hubert C. George, Nicole K. Thomas, Jeanette M. Roberts, Roman Caudillo, Zachary R. Yoscovits, Kanwaljit Singh, Roza Kotlyar, Patrick H. Keys, James S. Clarke
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Patent number: 11011693Abstract: Embodiments of the present disclosure describe integrated quantum circuit assemblies that include quantum circuit components pre-packaged, or integrated, with some other electronic components and mechanical attachment means for easy inclusion within a cooling apparatus. An example integrated quantum circuit assembly includes a package and mechanical attachment means for securing the package within a cryogenic chamber of a cooling apparatus. The package includes a plurality of components, such as a quantum circuit component, an attenuator, and a directional coupler, which are integral to the package. Such an integrated assembly may significantly speed up installation and may help develop systems for rapidly bringing up quantum computers.Type: GrantFiled: June 24, 2019Date of Patent: May 18, 2021Assignee: Intel CorporationInventors: Lester Lampert, Ravi Pillarisetty, Nicole K. Thomas, Hubert C. George, Jeanette M. Roberts, David J. Michalak, Roman Caudillo, Thomas Francis Watson, Stephanie A. Bojarski, James S. Clarke
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Publication number: 20210036110Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.Type: ApplicationFiled: December 17, 2017Publication date: February 4, 2021Applicant: Intel CorporationInventors: Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Ravi Pillarisetty, Kanwaljit Singh, Payam Amin, Hubert C. George, Jeanette M. Roberts, Roman Caudillo, David J. Michalak, Zachary R. Yoscovits, Lester Lampert
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Patent number: 10910488Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin has a first side face and a second side face, and the fin includes a quantum well layer; and a gate above the fin, wherein the gate extends down along the first side face.Type: GrantFiled: June 26, 2018Date of Patent: February 2, 2021Assignee: Intel CorporationInventors: Hubert C. George, Lester Lampert, James S. Clarke, Ravi Pillarisetty, Zachary R. Yoscovits, Nicole K. Thomas, Roman Caudillo, Kanwaljit Singh, David J. Michalak, Jeanette M. Roberts
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Patent number: 10879446Abstract: Embodiments of the present disclosure relate to quantum circuit assemblies implementing superconducting qubits, e.g., transmons, in which SQUID loops and portions of FBLs configured to magnetically couple to the SQUID loops extend substantially vertically. In contrast to conventional implementations, for a vertical SQUID according to various embodiments of the present disclosure, a line that is perpendicular to the SQUID loop is parallel to the qubit substrate. A corresponding FBL is also provided in a vertical arrangement, in order to achieve efficient magnetic coupling to the vertical SQUID loop, by ensuring that at least a portion of the FBL designed to conduct current responsible for generating magnetic field for tuning qubit frequency is substantially perpendicular to the substrate.Type: GrantFiled: August 14, 2018Date of Patent: December 29, 2020Assignee: Intel CorporationInventors: Roman Caudillo, Lester Lampert, David J. Michalak, Jeanette M. Roberts, Ravi Pillarisetty, Hubert C. George, Nicole K. Thomas, James S. Clarke
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Publication number: 20200403137Abstract: Embodiments of the present disclosure describe integrated quantum circuit assemblies that include quantum circuit components pre-packaged, or integrated, with some other electronic components and mechanical attachment means for easy inclusion within a cooling apparatus. An example integrated quantum circuit assembly includes a package and mechanical attachment means for securing the package within a cryogenic chamber of a cooling apparatus. The package includes a plurality of components, such as a quantum circuit component, an attenuator, and a directional coupler, which are integral to the package. Such an integrated assembly may significantly speed up installation and may help develop systems for rapidly bringing up quantum computers.Type: ApplicationFiled: June 24, 2019Publication date: December 24, 2020Inventors: Lester Lampert, Ravi Pillarisetty, Nicole K. Thomas, Hubert C. George, Jeanette M. Roberts, David J. Michalak, Roman Caudillo, Thomas Francis Watson, Stephanie A. Bojarski, James S. Clarke
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Publication number: 20200373351Abstract: Embodiments of the present disclosure propose qubit substrates, as well as methods of fabricating thereof and related device assemblies. In one aspect of the present disclosure, a qubit substrate includes a base substrate of a doped semiconductor material, and a layer of a substantially intrinsic semiconductor material over the base substrate. Engineering a qubit substrate in this manner allows improving coherence times of qubits provided thereon, while, at the same time, being sufficiently mechanically robust so that it can be efficiently used in large-scale manufacturing.Type: ApplicationFiled: September 18, 2017Publication date: November 26, 2020Applicant: Intel CorporationInventors: Jeanette M. Roberts, Wesley T. Harrison, Adel A. Elsherbini, Stefano Pellerano, Zachary R. Yoscovits, Lester Lampert, Ravi Pillarisetty, Roman Caudillo, Hubert C. George, Nicole K. Thomas, David J. Michalak, Kanwaljit Singh, James S. Clarke
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Patent number: 10847705Abstract: Embodiments of the present disclosure describe two approaches to providing flux bias line structures for superconducting qubit devices. The first approach, applicable to flux bias line structures that include at least one portion that terminates with a ground connection, resides in terminating such a portion with a ground connection that is electrically isolated from the common ground plane of a quantum circuit assembly. The second approach resides in providing a SQUID loop of a superconducting qubit device and a portion of the flux bias line structure over a portion of a substrate that is elevated with respect to other portions of the substrate. These approaches may be used or alone or in combination, and may improve grounding of and reduce crosstalk caused by flux bias lines in quantum circuit assemblies.Type: GrantFiled: February 15, 2018Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Lester Lampert, Adel A. Elsherbini, James S. Clarke, Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Kanwaljit Singh, Roman Caudillo, Zachary R. Yoscovits, Nicole K. Thomas, Hubert C. George, Stefano Pellerano
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Publication number: 20200365656Abstract: Disclosed herein are quantum dot devices and techniques. In some embodiments, a quantum computing processing device may include a quantum well stack, an array of quantum dot gate electrodes above the quantum well stack, and an associated array of selectors above the array of quantum dot gate electrodes. The array of quantum dot gate electrodes and the array of selectors may each be arranged in a grid.Type: ApplicationFiled: September 28, 2017Publication date: November 19, 2020Applicant: Intel CorporationInventors: Ravi Pillarisetty, Nicole K. Thomas, Abhishek A. Sharma, Hubert C. George, Jeanette M. Roberts, Zachary R. Yoscovits, Roman Caudillo, Kanwaljit Singh, James S. Clarke