Patents by Inventor Roman CAUDILLO
Roman CAUDILLO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200350423Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.Type: ApplicationFiled: September 28, 2017Publication date: November 5, 2020Applicant: Intel CorporationInventors: Ravi Pillarisetty, Van H. Le, Nicole K. Thomas, Hubert C. George, Jeanette Roberts, Payam Amin, Zachary R. Yoscovits, Roman Caudillo, James S. Clarke, Roza Kotlyar, Kanwaljit Singh
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Patent number: 10803396Abstract: Disclosed herein are superconducting qubit devices with Josephson Junctions utilizing resistive switching materials, i.e., resistive Josephson Junctions (RJJs), as well as related methods and quantum circuit assemblies. In some embodiments, an RJJ may include a bottom electrode, a top electrode, and a resistive switching layer (RSL) disposed between the bottom electrode and the top electrode. Using the RSLs in Josephson Junctions of superconducting qubits may allow fine tuning of junction resistance, which is particularly advantageous for optimizing performance of superconducting qubit devices. In addition, RJJs may be fabricated using methods that could be efficiently used in large-scale manufacturing, providing a substantial improvement with respect to approaches for forming conventional Josephson Junctions, such as e.g. double-angle shadow evaporation approach.Type: GrantFiled: June 19, 2018Date of Patent: October 13, 2020Assignee: Intel CorporationInventors: Zachary R. Yoscovits, Roman Caudillo, Ravi Pillarisetty, Hubert C. George, Adel A. Elsherbini, Lester Lampert, James S. Clarke, Nicole K. Thomas, Kanwaljit Singh, David J. Michalak, Jeanette M. Roberts
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Publication number: 20200321436Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous first rows and the plurality of second gates are arranged in electrically continuous second rows parallel to the first rows. Quantum dot devices according to various embodiments of the present disclosure are based on arranging first and second gates in hexagonal/honeycomb arrays.Type: ApplicationFiled: December 23, 2017Publication date: October 8, 2020Applicant: Intel CorporationInventors: Ravi Pillarisetty, Hubert C. George, Nicole K. Thomas, Jeanette M. Roberts, Roman Caudillo, Zachary R. Yoscovits, Kanwaljit Singh, Roza Kotlyar, Patrick H. Keys, James S. Clarke
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Publication number: 20200312963Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack and a plurality of linear arrays of gates above the quantum well stack to control quantum dot formation in the quantum well stack. An insulating material may be between a first linear array of gates and a second linear array of gates, the insulating material may be between individual gates in the first linear array of gates, and gate metal of the first linear array of gates may extend over the insulating material.Type: ApplicationFiled: March 27, 2019Publication date: October 1, 2020Applicant: Intel CorporationInventors: Stephanie A. Bojarski, Hubert C. George, Sarah Atanasov, Nicole K. Thomas, Ravi Pillarisetty, Lester Lampert, Thomas Francis Watson, David J. Michalak, Roman Caudillo, Jeanette M. Roberts, James S. Clarke
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Publication number: 20200312989Abstract: Disclosed herein are quantum dot devices with multiple layers of gate metal, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material above the quantum well stack, wherein the insulating material includes a trench; and a gate on the insulating material and extending into the trench, wherein the gate includes a first gate metal in the trench and a second gate metal above the first gate metal.Type: ApplicationFiled: March 26, 2019Publication date: October 1, 2020Applicant: Intel CorporationInventors: Hubert C. George, Sarah Atanasov, Ravi Pillarisetty, Lester Lampert, James S. Clarke, Nicole K. Thomas, Roman Caudillo, Kanwaljit Singh, David J. Michalak, Jeanette M. Roberts, Stephanie A. Bojarski
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Publication number: 20200295164Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a first gate above the quantum well stack, wherein the first gate includes a first gate metal; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal, and a material structure of the second gate metal is different from a material structure of the first gate metal; wherein the quantum well layer has a first strain under the first gate, a second strain under the second gate, and the first strain is different from the second strain.Type: ApplicationFiled: January 8, 2018Publication date: September 17, 2020Applicant: Intel CorporationInventors: Kanwaljit Singh, Ravi Pillarisetty, Nicole K. Thomas, Payam Amin, Roman Caudillo, Hubert C. George, Jeanette M. Roberts, Zachary R. Yoscovits, James S. Clarke, Lester Lampert, David J. Michalak
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Publication number: 20200279937Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include a quantum well stack, the quantum well stack includes a quantum well layer, the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack, and (1) gate metal of individual gates of the array of gates is tapered so as to narrow farther from the quantum well stack or (2) top surfaces of gate metal of individual gates of the array of gates are dished.Type: ApplicationFiled: December 23, 2017Publication date: September 3, 2020Applicant: Intel CorporationInventors: Ravi Pillarisetty, Willy Rachmady, Kanwaljit Singh, Nicole K. Thomas, Hubert C. George, Zachary R. Yoscovits, Roman Caudillo, Payam Amin, Jeanette M. Roberts, James S. Clarke
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Patent number: 10763347Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include: a quantum well stack having alternatingly arranged relaxed and strained layers; and a plurality of gates disposed above the quantum well stack to control quantum dot formation in the quantum well stack.Type: GrantFiled: December 14, 2016Date of Patent: September 1, 2020Assignee: Intel CorporationInventors: Payam Amin, Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Ravi Pillarisetty, Hubert C. George, Kanwaljit Singh, Van H. Le, Jeanette M. Roberts, Roman Caudillo, Zachary R. Yoscovits, David J. Michalak
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Publication number: 20200258984Abstract: Disclosed herein are quantum dot devices with conductive liners, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base, a first fin extending from the base, a second fin extending from the base, a conductive material between the first fin and the second fin, and a dielectric material between the conductive material and the first fin.Type: ApplicationFiled: February 13, 2019Publication date: August 13, 2020Applicant: Intel CorporationInventors: Hubert C. George, Ravi Pillarisetty, Lester Lampert, James S. Clarke, Nicole K. Thomas, Stephanie A. Bojarski, Roman Caudillo, David J. Michalak, Jeanette M. Roberts, Thomas Francis Watson
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Patent number: 10714604Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a first dielectric material around a bottom portion of the fin; and a second dielectric material around a top portion of the fin, wherein the second dielectric material is different from the first dielectric material.Type: GrantFiled: June 25, 2018Date of Patent: July 14, 2020Assignee: Intel CorporationInventors: Hubert C. George, David J. Michalak, Ravi Pillarisetty, Lester Lampert, James S. Clarke, Zachary R. Yoscovits, Nicole K. Thomas, Roman Caudillo, Kanwaljit Singh, Jeanette M. Roberts
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Publication number: 20200212210Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; an insulating material at least partially above the fin, wherein the insulating material includes a trench above the fin; and a gate metal on the insulating material and extending into the trench.Type: ApplicationFiled: December 21, 2017Publication date: July 2, 2020Applicant: Intel CorporationInventors: Ravi Pillarisetty, Nicole K. Thomas, Hubert C. George, Jeanette M. Roberts, Payam Amin, Zachary R. Yoscovits, Roman Caudillo, James S. Clarke
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Patent number: 10686007Abstract: Embodiments of the present disclosure propose quantum circuit assemblies with transmission lines and/or capacitors that include layer-conductors oriented perpendicular to a substrate (i.e. oriented vertically) or a qubit die, with at least portions of the vertical layer-conductors being at least partially buried in the substrate. Such layer-conductors may form ground and signal planes of transmission lines or capacitor plates of capacitors of various quantum circuit assemblies.Type: GrantFiled: June 20, 2018Date of Patent: June 16, 2020Assignee: Intel CorporationInventors: Hubert C. George, Adel A. Elsherbini, Lester Lampert, James S. Clarke, Ravi Pillarisetty, Zachary R. Yoscovits, Nicole K. Thomas, Roman Caudillo, Kanwaljit Singh, David J. Michalak, Jeanette M. Roberts
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Patent number: 10665769Abstract: Various embodiments of the present disclosure present quantum circuit assemblies implementing vertically-stacked parallel-plate capacitors. Such capacitors include first and second capacitor plates which are parallel to one another and separated from one another by a gap measured along a direction perpendicular to the qubit plane, i.e. measured vertically. Fabrication techniques for manufacturing such capacitors are also disclosed. Vertically-stacked parallel-plate capacitors may help increasing coherence times of qubits, facilitate use of three-dimensional and stacked designs for quantum circuit assemblies, and may be particularly advantageous for realizing device scalability and use of 300-millimeter fabrication processes.Type: GrantFiled: June 19, 2018Date of Patent: May 26, 2020Assignee: Intel CorporationInventors: Roman Caudillo, Zachary R. Yoscovits, Lester Lampert, David J. Michalak, Jeanette M. Roberts, Ravi Pillarisetty, Hubert C. George, Nicole K. Thomas, James S. Clarke
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Patent number: 10665770Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a gate above the fin; and a material on side faces of the fin; wherein the fin has a width between its side faces, and the fin is strained in the direction of the width.Type: GrantFiled: March 6, 2018Date of Patent: May 26, 2020Assignee: Intel CorporationInventors: Ravi Pillarisetty, Kanwaljit Singh, Patrick H. Keys, Roman Caudillo, Hubert C. George, Zachary R. Yoscovits, Nicole K. Thomas, James S. Clarke, Roza Kotlyar, Payam Amin, Jeanette M. Roberts
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Patent number: 10565515Abstract: Embodiments of the present disclosure describe quantum circuit assemblies utilizing triaxial cables to communicate signals to/from quantum circuit components. One assembly includes a cooling apparatus for cooling a quantum circuit component that includes at least one qubit device. The cooling apparatus includes at least one triaxial connector for providing signals to and/or receiving signals from the quantum circuit component using one or more triaxial cables. Other assemblies include quantum circuit components and various electronic components (e.g. attenuators, filters, or amplifiers) for use within the cooling apparatus, adapted to be used with triaxial cables by incorporating triaxial connectors as well.Type: GrantFiled: June 20, 2018Date of Patent: February 18, 2020Assignee: Intel CorporationInventors: Lester Lampert, Ravi Pillarisetty, Nicole K. Thomas, Hubert C. George, Jeanette M. Roberts, David J. Michalak, Roman Caudillo, Zachary R. Yoscovits, James S. Clarke
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Publication number: 20190392352Abstract: Embodiments of the present disclosure provide quantum circuit assemblies that implement adaptive programming of quantum dot qubit devices. An example quantum circuit assembly includes a quantum circuit component including a quantum dot qubit device, and a control logic coupled to the quantum circuit component. The control logic is configured to adaptively program the quantum dot qubit device by iterating a sequence of applying one or more signals to the quantum dot qubit device, determining a state of at least one qubit of the quantum dot qubit device, and using the determined state to modify the signals to be applied to the quantum dot qubit device in the next iteration. In this manner, the signals may be fine-tuned to achieve a higher probability of the qubit(s) in the quantum dot qubit device being set to the desired state.Type: ApplicationFiled: June 25, 2018Publication date: December 26, 2019Applicant: Intel CorporationInventors: Lester Lampert, Ravi Pillarisetty, Nicole K. Thomas, Hubert C. George, Jeanette M. Roberts, David J. Michalak, Roman Caudillo, Zachary R. Yoscovits, James S. Clarke
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Patent number: 10490727Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate and an adjacent second gate above the quantum well stack; and a gate wall between the first gate and the second gate, wherein the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.Type: GrantFiled: February 20, 2018Date of Patent: November 26, 2019Assignee: Intel CorporationInventors: Nicole K. Thomas, James S. Clarke, Willy Rachmady, Ravi Pillarisetty, Hubert C. George, Kanwaljit Singh, Jeanette M. Roberts, David J. Michalak, Roman Caudillo, Zachary R. Yoscovits, Lester Lampert
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Patent number: 10475912Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a layer of gate dielectric above the quantum well stack; a first gate metal and a second gate metal above the layer of gate dielectric; and a gate wall between the first gate metal and the second gate metal, wherein the gate wall is above the layer of gate dielectric, and the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.Type: GrantFiled: February 20, 2018Date of Patent: November 12, 2019Assignee: Intel CorporationInventors: Nicole K. Thomas, Ravi Pillarisetty, Kanwaljit Singh, Hubert C. George, Jeanette M. Roberts, David J. Michalak, Roman Caudillo, Zachary R. Yoscovits, Lester Lampert, James S. Clarke, Willy Rachmady
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Patent number: 10468578Abstract: An exemplary superconducting qubit device package includes a qubit die housing a superconducting qubit device that includes at least one resonator, and a package substrate, each having a first face and an opposing second face. The resonator is disposed on the first face of the qubit die. The first face of the qubit die faces and is attached to the second face of the package substrate by first level interconnects. The second face of the package substrate includes a superconductor facing at least portions of the resonator. Such a package architecture may advantageously allow reducing design complexity and undesired coupling, enable inclusion of larger numbers of qubit devices in the qubit die of the package, reduce potential negative impact of the materials used in the package substrate on resonator performance, and limit some sources of qubit decoherence.Type: GrantFiled: February 20, 2018Date of Patent: November 5, 2019Assignee: Intel CorporationInventors: Adel A. Elsherbini, Javier A. Falcon, Roman Caudillo, James S. Clarke
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Publication number: 20190334020Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include: a quantum well stack having alternatingly arranged relaxed and strained layers; and a plurality of gates disposed above the quantum well stack to control quantum dot formation in the quantum well stack.Type: ApplicationFiled: December 14, 2016Publication date: October 31, 2019Applicant: Intel CorporationInventors: Payam Amin, Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Ravi Pillarisetty, Hubert C. George, Kanwaljit Singh, Van H. Le, Jeanette M. Roberts, Roman Caudillo, Zachary R. Yoscovits, David J. Michalak