Abstract: A semiconductor device tester includes a parametric measurement unit (PMU) stage for producing a DC test signal and a pin electronics (PE) stage for producing an AC test signal to test a semiconductor device. A driver circuit is capable of providing a version of the DC test signal and a version of the AC test signal to the semiconductor device.

Abstract: A method and apparatus is provided to recover clock information embedded in a digital signal such as a data signal. A set of strobe pulses can be generated by routing an edge generator to a delay elements with incrementally increasing delay values. A set of latches triggered by incrementally delayed signals from the edge generator can capture samples of the data signal. An encoder can convert the samples to a word representing edge time and polarity of the sampled signal. The word representing edge time can be stored in memory. An accumulator can collect the average edge time over N samples. The average edge time can be adjusted with a fixed de-skew value to form the extracted clock information. The extracted clock information can be used as a pointer to the words stored in memory.

Abstract: A test system timing method simulates the timing of a synchronous clock on the device under test. Strobe pulses can be generated by routing an edge generator to delay elements with incrementally increasing delay values. A data signal or synchronous clock signal can be applied to the input of each of a set of latches which are clocked by the strobe pulses. An encoder can convert the series of samples which are thereby latched to a word representing edge time and polarity of the sampled signal. If the sampled signal is a data signal, the word can be stored in memory. If the sampled signal is a clock signal, the word is routed to a clock bus and used to address the memory. The difference between clock edge time and data edge time is provided and can be compared against expected values.

Abstract: Circuitry for driving a pin of a device includes a first circuit path terminating in a first impedance, a second circuit path terminating in a second impedance, where the second impedance is less than the first impedance, and a selection circuit to control operation of the second circuit path. When the second circuit path is not configured for operation, the first circuit path is configured to output one of plural first voltage signals. When the second circuit path is in configured for operation, the second circuit path is configured to output a second voltage signal. The second voltage signal is greater than the plural first voltage signals.

Abstract: A system and apparatus generates a time-stamp to identify and record the time of an event such as an edge received in a data signal or clock signal. A set of strobe pulses can be generated by routing an external clock signal to delay elements with incrementally increasing delay values. A data signal or device under test clock signal can be applied to the input to each of a set of latches which are clocked by the strobe pulses. The set of latches can thereby capture a series of samples of the data signal or clock signal. The series of samples can be encoded as an edge time within a clock cycle. A clock cycle counter can be added to the edge time to generate the time stamp.

Abstract: Circuitry for driving a pin includes a first resistive circuit connected to the pin, a first transistor circuit to connect the first resistive circuit to a logic level voltage in response to a trigger voltage, the first transistor circuit and the first resistive circuit together defining a termination impedance, and a driver circuit to apply the trigger voltage to the first transistor circuit. The driver circuit includes counterparts to the first resistive circuit and the first transistor circuit. The counterparts define a counterpart impedance that is controlled to control the trigger voltage and thereby control the termination impedance.

Abstract: A semiconductor device tester includes a parametric measurement unit (PMU) driver circuit that provides a DC test signal for testing a semiconductor device, and a feedback circuit that senses the DC test signal at an output of the PMU driver circuit and sends the sensed DC test signal to an input of the PMU driver circuit for compensating the DC test signal.

Abstract: A method of and system for producing signals to test semiconductor devices includes a pin electronic (PE) stage for providing a parametric measurement unit (PMU) current test signal to a semiconductor device under test. The PE stage also senses a response from the semiconductor device under test.

Abstract: In one aspect, the invention is an integrated circuit (IC) for use in testing a device. The IC includes a pin electronics (PE) driver having an output and a pin. The IC also includes a buffer connected to the output of the PE driver and the pin. The first voltage measured at the pin is greater than a second voltage measured at the output. The IC may include a first amplifier having an input connected to a voltage source. The IC may also include a second amplifier having an input connected to the output of the PE driver.

Abstract: In one aspect, the invention is an integrated circuit (IC) for use in testing a device. The IC includes a pin electronics (PE) driver having an output and a pin. The IC also includes a buffer connected to the output of the PE driver and the pin. The first voltage measured at the pin is greater than a second voltage measured at the output. The IC may include a first amplifier having an input connected to a voltage source. The IC may also include a second amplifier having an input connected to the output of the PE driver.

Abstract: A semiconductor device tester includes a parametric measurement unit (PMU) stage for producing a DC test signal and a pin electronics (PE) stage for producing an AC test signal to test a semiconductor device. A driver circuit is capable of providing a version of the DC test signal and a version of the AC test signal to the semiconductor device.

Abstract: In one aspect, the invention is an integrated circuit (IC) for use in testing an analog-to-digital (ADC) converter includes a first channel of a parametric measurement unit (PMU) configured to send a force signal to the ADC. The IC also includes a first digital-to-analog converter (DAC) connected to the first channel of the PMU. The DAC has a DC level of accuracy of less than 1 millivolt. In another aspect, the invention is an integrated circuit (IC) for use in testing a digital-to-analog-converter-device-under-test (DACDUT). The IC includes a first channel of a parametric measurement unit (PMU) configured to send a force signal to the DACDUT and including an output port for taking measurements, a first digital-to-analog converter (DAC) connected to the first channel of the PMU and a PMU measurement path connected to the output port having a DC level of accuracy of less than 1 mV.

Abstract: A accurate time measurement circuit. The design is amenable to implementation as a CMOS integrated circuits, making the circuit suitable for a highly integrated system, such as automatic test equipment where multiple time measurement circuits are required. The circuit uses a delay locked loop to generate a plurality of signals that are delayed in time by an interval D. The signal to be measured is fed to a bank of delay elements, each with a slightly different delay with the difference in delay between the first and the last being more than D. An accurate time measurement is achieved by finding coincidence between one of the TAP signals and one of the delay signals. The circuit has much greater accuracy than a traditional delay line based time measurement circuit with the same number of taps. It therefore provides both accuracy and fast re-fire time and is less susceptible to noise.

Abstract: An automatic test system for testing semiconductor devices. The test system includes time measurement circuitry. The time measurement circuitry can be programmed to operate in a single-shot mode or a higher resolution, repetitive-measurement mode. To simplify the design and construction of the system, the same time measurement circuit is used in both measurement modes. To provide higher resolution in the repetitive measurement mode, variation is introduced into the signal to be measured and resulting measurements are averaged. Any bias introduced by the variation is subtracted from the averaged value.

Abstract: A tester that is well suited for operation at high speeds or with narrow pulses. The tester includes a state based pulse shaping circuit that combines edge signals into a pulsed output signal. The circuit combines groups of set and reset signals. The edge signals define the start and stop of pulses in the output signal even if the set and reset edge signals overlap or successive set signals overlap or successive reset signals overlap. This circuit allows for a low cost and low power CMOS implementation of an output signal formatter.

Abstract: A tester that is well suited for operation at high speeds or with narrow pulses. The tester includes a state based pulse shaping circuit that combines edge signals into a pulsed output signal. The circuit combines groups of set and reset signals. The edge signals define the start and stop of pulses in the output signal even if the set and reset edge signals overlap or successive set signals overlap or successive reset signals overlap. This circuit allows for a low cost and low power CMOS implementation of an output signal formatter.

Abstract: A accurate time measurement circuit. The design is amenable to implementation as a CMOS integrated circuits, making the circuit suitable for a highly integrated system, such as automatic test equipment where multiple time measurement circuits are required. The circuit uses a delay locked loop to generate a plurality of signals that are delayed in time by an interval D. The signal to be measured is fed to a bank of delay elements, each with a slightly different delay with the difference in delay between the first and the last being more than D. An accurate time measurement is achieved by finding coincidence between one of the TAP signals and one of the delay signals. The circuit has much greater accuracy than a traditional delay line based time measurement circuit with the same number of taps. It therefore provides both accuracy and fast re-fire time and is less susceptible to noise.

Abstract: A semiconductor structure for controlling the temperature of a component is described. The structure includes a resistive layer having one or more channels provided therein and having a resistance characteristic such that a signal applied thereto causes the resistive layer to generate heat. A cooling fluid is fed through the one or more channels to cool both the structure and a component disposed on the structure. By providing the cooling channels in the resistive layer, the heating and cooling sources are intermingled. The structure can optionally include precising and vacuum clamping structures, to locate and hold the component that is to be temperature controlled.

Abstract: Pin slice circuitry used in automatic test equipment is disclosed. The pin slice circuitry includes a portion implemented using CMOS technology and a portion implemented using bipolar technology. The CMOS portion includes a plurality of timing generator circuits, digital sigma delta modulator circuitry used to generate digital bit streams representative of analog reference levels, and programmable digital signal processing circuitry. The bipolar portion includes driver/receiver channels, a parametric measurement unit, and decoder circuitry, which produces the analog reference levels from the digital bit streams generated by the modulator circuitry. The analog reference levels are used by the driver/receiver channels and the parametric measurement unit; and, the digital signal processing circuitry is used to monitor and control levels produced by the parametric measurement unit. The disclosed pin slice circuitry has the advantages of reduced size and cost as compared with conventional pin slice circuitry.

Abstract: Automatic test equipment suitable for testing high speed semiconductor devices. The test equipment includes a formatter circuit with a flip flop that produces an output in the desired format even if the edge signals that control the setting and resetting of the flip flop overlap. The flip flop allows the test system to generate outputs with narrow pulses, and can generate output pulses that are narrower than the controlling edge signals.