Abstract: Pin slice circuitry used in automatic test equipment is disclosed. The pin slice circuitry includes a portion implemented using CMOS technology and a portion implemented using bipolar technology. The CMOS portion includes a plurality of timing generator circuits and sigma delta modulator circuitry, which is used to generate digital bit streams representative of analog reference levels. The bipolar portion includes driver/receiver channels, a parametric measurement unit, and decoder circuitry, which produces the analog reference levels from the digital bit streams generated by the modulator circuitry. The analog reference levels are used by the driver/receiver channels and the parametric measurement unit. The disclosed pin slice circuitry has the advantages of reduced size and cost as compared with conventional pin slice circuitry.

Abstract: Automatic test equipment for semiconductor devices. The automatic test equipment contains numerous channels of electronic circuitry in which precisely timed test signals are generated. Significant advantages in both cost and size are achieved by incorporating multiple channels on one integrated circuit chip. To allow this level of integration without degrading timing accuracy, a series of design techniques are employed. These techniques include the use of guard rings and guard layers, placement of circuit elements in relation to the guard rings and guard layers, separate signal traces for power and ground for each channel, and circuit designs that allow the voltage across a filter capacitor to define a correction signal. Another feature of the disclosed embodiment is a fine delay element design that can be controlled for delay variations and incorporates calibration features. A further disclosed feature is circuitry that allows the tester to have a short refire recovery time.