Abstract: An Ethernet adapter is disclosed. The Ethernet adapter comprises a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor. The plurality of layers include a demultiplexing mechanism to allow for partitioning of the processor. A Host Ethernet Adapter (HEA) is an integrated Ethernet adapter providing a new approach to Ethernet and TCP acceleration. A set of TCP/IP acceleration features have been introduced in a toolkit approach: Servers TCP/IP stacks use these accelerators when and as required. The interface between the server and the network interface controller has been streamlined by bypassing the PCI bus. The HEA supports network virtualization. The HEA can be shared by multiple OSs providing the essential isolation and protection without affecting its performance.

Abstract: A light fixture (200) comprises a mounting fixture (501) that is configured and arranged to facilitate mounting the light fixture to a mounting surface other than ground along with at least a first light socket (502) and a plurality of permanently mounted light emitting diodes (LED's) (503). The light socket and the LED's are supported by the mounting fixture. The LED's are configured in an array and are oriented towards the mounting surface when the light fixture is installed on the mounting surface. This light fixture can further comprise an ambient light sensor (504), an animate object detector (505), and/or a timer (506). The wall-washing LED's can be switched on and off automatically (103) to provide the desired decorative effect during the evening hours. In addition, the light socket can be rendered controllable (105) as a function of whether it is dark out and whether an animate object has been detected.

Abstract: An electronic Input/Output Interface and device abstraction system used in gaming machines includes: a game central processing unit (game “CPU”); an intelligent input/output controller board (“IOCB”); an Industry Standard Architecture PC bus (“ISA” bus); and a framed message transport protocol. The IOCB facilitates communications between the game CPU and virtual device services, which are peripheral devices associated with the gaming system. The game CPU communicates to gaming peripherals by sending virtual device messages across the ISA bus to the IOCB. The IOCB routes virtual device messages to appropriate virtual device services. Virtual device services are responsible for handling specific hardware, and include virtual device drivers on the game CPU that communicate with virtual devices on the IOCB. Use of the IOCB and the high speed interface enables the game CPU to use more of its available functions for controlling gaming functions rather than one operation of its associated peripheral devices.

Abstract: An aliased queue pair is provided within a logically partitioned data processing system for each logical partition for the single general services management queue pair that exists within a physical host channel adapter. Packets intended for the logical ports are received at the physical port. Multiple partitions exist within the data processing system. When one of these partitions needs to use one of the logical ports, a queue pair is selected. The queue pair is then associated with the logical port. The queue pair is configured as an aliased general services management queue pair and is used by the partition as if the aliased queue pair were the single general services management queue pair provided in the channel adapter.

Abstract: A multiprocessor system which includes automatic workload distribution. As threads execute in the multiprocessor system, an operating system or hypervisor continuously learns the execution characteristics of the threads and saves the information in thread-specific control blocks. The execution characteristics are used to generate thread performance data. As the thread executes, the operating system continuously uses the performance data to steer the thread to a core that will execute the workload most efficiently.

Abstract: A method and apparatus tracks packets and reliably transmits data over a computer transmission system with a reduced amount of memory needed in the transmission interface. The invention eliminates the need to keep all the packets of data queued until the acknowledge message for that data has arrived. Instead, it keeps track of how many packets have been sent and which packets correspond to the end of a message, marking them off when acknowledge messages are received. If packets are lost, the invention determines which packet were lost, backs up to the lost packet, re-fetches the data and resends it. Embodiments of the present invention eliminate the need to queue packets, reducing silicon size and allowing the available bandwidth of the output bus to be more fully utilized.

Abstract: Error diffusion is performed upon input image data. In one aspect, multiple error diffusion processing elements perform error diffusion on a selected pixel in parallel. In another aspect, the error diffusion logic is integrally formed with a fast local memory in the same electronic device, such as an ASIC. The error data produced by the error diffusion logic for a pixel is buffered in the fast local memory until it is to be used by the error diffusion logic on other pixels. In still another aspect, a first-in-first-out (FIFO) buffer regulates or buffers the color image data between the output of a color conversion system, such as a colorant lookup table, and the input an error diffusion processing element. In yet another aspect, the error diffusion logic has tagging logic that produces and stores an indicator, either in the output data stream itself or in a separate area, to indicate whether a raster contains printable data.

Abstract: Apparatus for providing a checksum in a network transmission. In one aspect of the invention, a checksum for a packet to be transmitted on a network is determined by retrieving packet information from a storage device, the packet information to be included in the packet to be transmitted. A blind checksum value is determined based on the retrieved packet information, and the blind checksum value is adjusted to a protocol checksum based on descriptor information describing the structure of the packet. The protocol checksum is inserted in the packet before the packet is transmitted.

Abstract: A method for performing a lookup for a packet in a computer network are disclosed. The packet includes a header. The method includes providing a parser, providing a lookup engine coupled with the parser, and providing a processor coupled with the lookup engine. The parser is for parsing the packet for the header prior to receipt of the packet being completed. The lookup engine performs a lookup for the header and returns a resultant. In one aspect, the lookup includes performing a local lookup of a cache that includes resultants of previous lookups. The processor processes the resultant.

Abstract: An adapter includes registers, a local context table, and logic that allows copying hardware context structures from a first location in memory to a second location in memory while the computer system continues to run. The local context table in the adapter is loaded with a desired block of context entries from the first location in memory. Values in the registers cause the adapter to write this desired block of context entries to the second location in memory in a way that does not inhibit the operation of the computer system.

Abstract: The present invention provides miniature power supplies and circuitry for powering high-voltage devices.

Abstract: A fortune telling device is disclosed that may be consulted while playing poker. The device is hollow, and simulates a stack of poker chips. A cube with alternate, distinct betting choices on each side floats within a liquid medium within the hollow wall. When playing poker, the player may consults the device by shaking, and allowing the floating cube to rise to the surface, when a betting choice must be made. In this manner, the pleasure of playing the game of chance is enhanced without the need of high-stakes gambling.

Abstract: An electronic Input/Output Interface and device abstraction system used in gaming machines includes: a game central processing unit (game “CPU”); an intelligent input/output controller board (“IOCB”); an Industry Standard Architecture PC bus (“ISA” bus); and a framed message transport protocol. The IOCB facilitates communications between the game CPU and virtual device services, which are peripheral devices associated with the gaming system. The game CPU communicates to gaming peripherals by sending virtual device messages across the ISA bus to the IOCB. The IOCB routes virtual device messages to appropriate virtual device services. Virtual device services are responsible for handling specific hardware, and include virtual device drivers on the game CPU that communicate with virtual devices on the IOCB. Use of the IOCB and the high speed interface enables the game CPU to use more of its available functions for controlling gaming functions rather than one operation of its associated peripheral devices.

Abstract: A system for performing a lookup for a packet in a computer network are disclosed. The packet includes a header. The system includes a parser, a lookup engine coupled with the parser, and a processor coupled with the lookup engine. The parser parses the packet for the header prior to receipt of the packet being completed. The lookup engine performs a lookup for the header and returns a resultant. In one aspect, the lookup includes performing a local lookup of a cache that includes resultants of previous lookups. The processor processes the resultant.

Abstract: An ultrasonic nozzle for applying a coating to an exterior surface of a substrate. The ultrasonic nozzle has an ultrasonic nozzle having an amplitude. The amplitude is greater than 120 microns.

Abstract: A method to eject a fluid from a surface. The steps of the method are i.) vibrating a surface of a nozzle in a direction substantially normal to the surface and ii.) providing an amplitude of the vibration that is equal to or greater than about 120 microns.

Abstract: A method, computer program product, and data processing system for providing system-area network (SAN) multicasting functionality in a logically partitioned (LPAR) data processing system in which a channel adapter is shared among a plurality of logical partitions is disclosed. A preferred embodiment of the present invention allows LPAR “hypervisor” firmware to assume the responsibility for multicast protocol handling and distribution of packets among logical partitions.

Abstract: Field is ejected from a surface of an apparatus. The apparatus comprises a.) a power supply operating at a frequency; b.) a transducer, which upon being applied the power is made to vibrate with a first amplitude; c.) a vibrating nozzle, comprising the surface, which is acoustically coupled to the transducer, to transmit the transducer vibration to the surface with a second amplitude; and, d.) a control unit to control the power supply applied to the transducer. The fluid is delivered to the surface of the nozzle. During this time the control unit cycles the power applied to the transducer at the frequency between a low power level and a high power level. The fluid is ejected from the surface when the high power level (i.e., first power level) is applied to the transducer but not when the low power level (i.e., second power level) is applied to the transducer.

Abstract: A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.

Abstract: An adapter includes registers, a local context table, and logic that allows copying hardware context structures from a first location in memory to a second location in memory while the computer system continues to run. The local context table in the adapter is loaded with a desired block of context entries from the first location in memory. Values in the registers cause the adapter to write this desired block of context entries to the second location in memory in a way that does not inhibit the operation of the computer system.