Abstract: A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.

Abstract: The present invention pertains to films comprising silicon and oxygen that are doped with carbon and the use of the films in integrated circuit technology, such as capacitor constructions, DRAM constructions, semiconductive material assemblies, etching processes, and methods for forming capacitors, DRAMs and semiconductive material assemblies.

Abstract: The present invention provides a method for improving the erase speed and the uniformity of erase characteristics in erasable programmable read-only memories. This result is achieved by forming polycrystalline floating gate layers with optimized grain size on a tunnel dielectric layer. Nucleation sites are formed by exposing the tunnel dielectric layer to a first set of conditions including a first temperature and a first atmosphere selected to optimize nucleation site size and distribution density across the tunnel dielectric layer. A polycrystalline floating gate layer is formed on top of the nucleation sites by exposing the nucleation sites to a second set of conditions including a second temperature and a second atmosphere selected to optimize polycrystalline grain size and distribution density across the polycrystalline floating gate layer.

Abstract: A composite barrier layer formed between a glass film and active regions of a memory device is disclosed. The composite barrier layer comprises an oxide layer formed by atomic deposition process and an insulating layer, for example a nitride barrier layer, formed over the oxide layer. The composite barrier layer eliminates the diffusion of impurity atoms from the glass film into the active regions of the device.

Abstract: Methods for monitoring power supplied to a substrate to form a doped or undoped crystalline semiconductor material are disclosed. The methods include providing a layer of an amorphous semiconductor material, doped or undoped, on a substrate and heating the substrate while monitoring the power applied to a heating element to heat the substrate so as to maintain a desired temperature. A decrease in the power supplied to the substrate is indicative of a conversion of the amorphous semiconductor material to a crystalline form thereof, at which time the power supplied to the heating element is terminated. By selecting the degree of crystallinity of the layer of doped or undoped amorphous semiconductor material on a substrate, the grain size of the resulting crystalline material can be controlled.

Abstract: The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide-nitride-oxide or ONO) is enhanced in the dilute steam oxidation.

Abstract: A method for conditioning or repairing a dielectric structure of a semiconductor device structure with selectivity over an adjacent conductive or semiconductive structure of the semiconductor device structure, such as a capacitor dielectric and an adjacent bottom electrode of the capacitor. The method includes exposing the dielectric structure and at least an adjacent surface of the conductive or semiconductive structure to an oxidizing atmosphere that includes at least one oxidant and hydrogen species. The at least one hydrogen species adsorbs to a surface of the conductive or semiconductive structure so as to substantially prevent passage of the at least one oxidant into or through the conductive or semiconductive structure. The oxidant oxidizes or repairs voids or other defects that may be present in the dielectric structure. Semiconductor device structures fabricated by employing the method are also disclosed.

Abstract: The present invention provides a flash memory cell utilizing an ambient containing atomic oxidation for fabrication of a second or top oxide layer in a oxide-nitride-oxide insulating structure. The second or top oxide layer is grown utilizing atomic oxygen containing ambients. A silicon nitride is thus oxidized substantially faster than standard steam or oxygen ambients.

Abstract: Methods and devices are disclosed utilizing a silicon-containing barrier layer. A method of forming a barrier layer on a semiconductor device is disclosed. A semiconductor device is provided. A silicon-containing material is deposited on the semiconductor device. The silicon-containing material is processed in a reactive ambient. The barrier layer can be made primarily oxide, primarily nitride or both by the reactive ambient selected. A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate oxide, a silicon-containing barrier layer and a gate electrode. The gate oxide is formed over the substrate. The silicon-containing barrier layer is formed over the gate oxide by causing silicon atoms of a precursor layer react with a reactive agent. The gate electrode is formed over the silicon-containing barrier layer. Other embodiments utilizing a barrier layer are disclosed.

Abstract: A passivation method includes disassociating ammonia so as to expose at least interfaces between silicon-containing and passivation structures to at least hydrogen species derived from the ammonia and forming an encapsulant layer that is positioned so as to substantially contain the hydrogen species in the presence of the interfaces. The hydrogen passivation reduces a concentration of dangling silicon bonds at the interfaces by as much as about two orders of magnitude or greater. The encapsulant layer, which may include silicon nitride, prevents hydrogen species from escaping therethrough as high temperature processes are subsequently conducted. Once high temperature processes have been completed, portions of the encapsulant layer may be removed, as needed, to provide access to features of the semiconductor device structure that underlie the encapsulant layer. Semiconductor device structures that have been passivated in such a manner are also disclosed.

Abstract: Methods and devices are disclosed utilizing a silicon-containing barrier layer. A method of forming a barrier layer on a semiconductor device is disclosed. A semiconductor device is provided. A silicon-containing material is deposited on the semiconductor device. The silicon-containing material is processed in a reactive ambient. The barrier layer can be made primarily oxide, primarily nitride or both by the reactive ambient selected. A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate oxide, a silicon-containing barrier layer and a gate electrode. The gate oxide is formed over the substrate. The silicon-containing barrier layer is formed over the gate oxide by causing silicon atoms of a precursor layer react with a reactive agent. The gate electrode is formed over the silicon-containing barrier layer. Other embodiments utilizing a barrier layer are disclosed.

Abstract: A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.

Abstract: A conductive structure for use in a semiconductor device includes a multilayer structure. A first layer includes a material containing silicon, e.g., polysilicon and silicon germanide. A barrier layer is formed over the first layer, with the barrier layer including metal silicide or metal silicide nitride. A top conductive layer is formed over the barrier layer. The top conductive layer can include metal or metal suicide. Selective oxidation can be performed to reduce the amount of oxidation of selected materials in a structure containing multiple layers, such as the multilayer conductive structure. The selective oxidation is performed in a single-wafer rapid thermal processing system, in which a selected ambient, including hydrogen, is used to ensure low oxidation of a selected material, such as tungsten or a metal nitride.

Abstract: Methods and devices are disclosed utilizing a silicon-containing barrier layer. A method of forming a barrier layer on a semiconductor device is disclosed. A semiconductor device is provided. A silicon-containing material is deposited on the semiconductor device. The silicon-containing material is processed in a reactive ambient. The barrier layer can be made primarily oxide, primarily nitride or both by the reactive ambient selected. A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate oxide, a silicon-containing barrier layer and a gate electrode. The gate oxide is formed over the substrate. The silicon-containing barrier layer is formed over the gate oxide by causing silicon atoms of a precursor layer react with a reactive agent. The gate electrode is formed over the silicon-containing barrier layer. Other embodiments utilizing a barrier layer are disclosed.

Abstract: The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide-nitride-oxide or ONO) is enhanced in the dilute steam oxidation.

Abstract: A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.

Abstract: A conductive structure for use in a semiconductor device includes a multilayer structure. A first layer includes a material containing silicon, e.g., polysilicon and silicon germanide. A barrier layer is formed over the first layer, with the barrier layer including metal silicide or metal silicide nitride. A top conductive layer is formed over the barrier layer. The top conductive layer can include metal or metal silicide. Selective oxidation can be performed to reduce the amount of oxidation of selected materials in a structure containing multiple layers, such as the multi-layer conductive structure. The selective oxidation is performed in a single-wafer rapid thermal processing system, in which a selected ambient, including hydrogen, is used to ensure low oxidation of a selected material, such as tungsten or a metal nitride.

Abstract: A conductive structure for use in a semiconductor device includes a multilayer structure. A first layer includes a material containing silicon, e.g., polysilicon and silicon germanide. A barrier layer is formed over the first layer, with the barrier layer including metal silicide or metal silicide nitride. A top conductive layer is formed over the barrier layer. The top conductive layer can include metal or metal silicide. Selective oxidation can be performed to reduce the amount of oxidation of selected materials in a structure containing multiple layers, such as the multilayer conductive structure. The selective oxidation is performed in a single-wafer rapid thermal processing system, in which a selected ambient, including hydrogen, is used to ensure low oxidation of a selected material, such as tungsten or a metal nitride.

Abstract: A method for reliably forming polysilicon of a desired surface roughness includes providing a layer of doped or undoped amorphous silicon on a substrate and heating said substrate while monitoring the emission of said substrate and comparing the monitored emission with an expected emission attributable to the heating regime employed. An increase in the monitored emission not attributable to the heating regime signals a transition of the layer of amorphous silicon to rough polysilicon. A decrease in the monitored emission not attributable to the heating regime signals a transition to smooth polysilicon. The increases and decreases in the monitored emission can be used to end the heating regime at the time at which the desired surface roughness of polysilicon is formed, or merely to passively monitor the process. The power supplied to heat the substrate to a desired temperature can also be monitored, in that a drop in required power is indicative of the formation of polysilicon.

Abstract: The present invention pertains to films comprising silicon and oxygen that are doped with carbon and the use of the films in integrated circuit technology, such as capacitor constructions, DRAM constructions, semiconductive material assemblies, etching processes, and methods for forming capacitors, DRAMs and semiconductive material assemblies.