Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

Abstract: A preparation method of a rice straw biochar loaded with Bacillus cereus, comprising: (1) washing, drying, grinding and sieving rice straws; (2) performing anaerobic pyrolysis treatment on the rice straws treated in the step (1) at 300-700° C. to obtain a biochar; (3) treating the biochar obtained in the step (2) with hydrochloric acid, then washing until a washing solution is neutral, drying, grinding, sieving and sterilizing to obtain a sterilized biochar; and (4) performing mixed culture on the sterilized biochar and a solution of Bacillus cereus subjected to activation culture, and then centrifuging after the end of culture to remove supernatant, so as to obtain a rice straw biochar loaded with Bacillus cereus having a carbon immobilizing capability.

Abstract: Peptidomimetic inhibitors of protein N-terminal methyltransferase 1, such as a compound with the following formula: a composition comprising same, and a method of use.

Abstract: A method and a system for dynamically tuning thermal design power and a non-transitory computer-readable storage medium are described. The system is configured to dynamically tune turbo boost mode operation parameters of a central processing unit (CPU), independent of related settings of a turbo boost operation state of the CPU. In an embodiment, a controller is configured to send a power tuning signal to a basic input/output system (BIOS) to directly intervene and tune a real-time operating power of the CPU.

Abstract: A time-interleaved analog-to-digital converter includes sampling circuits, amplifier circuits, analog-to-digital converter circuits, and a detector circuitry. The sampling circuits are configured to an input signal according to first clock signals, to generate first signals. The amplifier circuits are configured to generate second signals according to the first signals. The analog-to-digital converter circuits are configured to convert the second signals to generate a digital signals. The detector circuitry is configured to adjust a delay time of each of the first clock signals, and calibrate gains of the amplifier circuits according to the digital signals.

Abstract: A semiconductor structure includes a semiconductor substrate, a first source/drain portion, a second source/drain portion, a first metal contact, a second metal contact and a first conductive carbon layer. The first and second source/drain portions are formed over the semiconductor substrate, and are spaced apart from each other. The first source/drain portion has a conductivity type different from that of the second source/drain portion. The first and second metal contacts are respectively formed on the first and second source/drain portions. The first conductive carbon layer is formed between the first source/drain portion and the first metal contact.

Abstract: Method to implement heat dissipation multilayer and reduce thermal boundary resistance for high power consumption semiconductor devices is provided. The heat dissipation multilayer comprises a first crystalline layer that possesses a first phonon frequency range, a second crystalline layer that has a second phonon frequency range which does not overlap with the first phonon frequency range, and an amorphous layer located between the first and second crystalline layers. The amorphous layer has a third phonon frequency range that overlaps both the first and second phonon frequency ranges.

Abstract: A compound with the following formula (I) or a pharmaceutically acceptable salt thereof; a pharmaceutical composition comprising a compound of formula (I); and a method of inhibiting nicotinamide N-methyItransferase in a patient in need thereof, such as a patient with cancer.

Abstract: A feedback loop circuit of a voltage regulator includes a loadline and a compensation circuit. The loadline generates a feedback signal according to a sensed current signal that provides information of an inductor current of the voltage regulator, and outputs the feedback signal to a controller circuit of the voltage regulator for regulating an output voltage of the voltage regulator. The compensation circuit generates a compensation signal to compensate for a deviation of the output voltage, wherein the feedback signal generated from the loadline is affected by the compensation signal.

Abstract: A page switching method performed by a page switching apparatus includes: displaying a second page and creating a first display control in response to a first trigger operation on a first page; displaying the first display control at an upper layer of the second page; displaying the first page and creating a second display control in response to a selection operation on the first display control displayed at the upper layer of the second page; and displaying the second display control at an upper layer of the first page. The first display control is configured to provide an entry to the first page; and the second display control is configured to provide an entry to the second page.

Abstract: The present invention belongs to the technical field of membrane-based water treatment and relates to a novel guanidine-based composite nanofiltration (NF) flat-sheet membrane, and a preparation method and application thereof. The present invention provides a method for preparing a guanidine-based composite NF flat-sheet membrane, where a dense separation layer is formed on the surface of a polyethersulfone ultrafiltration membrane through polymerization reaction between the amino group of 1,3-diaminoguanidine and the acyl chloride group of trimesoyl chloride. Under suitable reaction conditions, the guanidine-based composite NF membrane obtained according to the present invention enables effective separation of multivalent ions over a wide pH range, with a rejection rate of over 96% for 1000 ppm of MgSO4 solution, and can operate continuously and stably in a mixed ions solution with a wide pH.

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of finFETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Abstract: A semiconductor device structure and methods of forming the same are described. In some embodiments, the structure includes an N-type source/drain epitaxial feature disposed over a substrate, a P-type source/drain epitaxial feature disposed over the substrate, a first silicide layer disposed directly on the N-type source/drain epitaxial feature, and a second silicide layer disposed directly on the P-type source/drain epitaxial feature. The first and second silicide layers include a first metal, and the second silicide layer is substantially thicker than the first silicide layer. The structure further includes a third silicide layer disposed directly on the first silicide layer and a fourth silicide layer disposed directly on the second silicide layer. The third and fourth silicide layer include a second metal different from the first metal, and the third silicide layer is substantially thicker than the fourth silicide layer.

Abstract: A semiconductor structure includes a semiconductor substrate, a first source/drain portion, a second source/drain portion, a first metal contact, a second metal contact and a first conductive carbon layer. The first and second source/drain portions are formed over the semiconductor substrate, and are spaced apart from each other. The first source/drain portion has a conductivity type different from that of the second source/drain portion. The first and second metal contacts are respectively formed on the first and second source/drain portions. The first conductive carbon layer is formed between the first source/drain portion and the first metal contact.

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Abstract: The present disclosure discloses a device with a protective layer, including a substrate, a seed layer formed on the substrate, and a diamond-like carbon layer formed on the seed layer, where the seed layer is a silicon nitride layer, and a content of nitrogen in the silicon nitride layer is 9%-17%. The present disclosure further discloses a microwave-assisted magnetic recording (MAMR) head slider, a head gimbal assembly, and a disk drive unit. The device has good thermal stability, oxidation resistance and corrosion resistance, thereby improving reliability and prolonging service life of an MAMR head.

Abstract: The present utility model belongs to the technical field of charging cases, and discloses a light guide structure of an earphone charging case, including a charging case and earphones. A shell of the charging case is provided with a shell light guide element, and the element penetrates the shell. The earphone is provided with a light source. When the earphone is placed in the charging case, light generated by the earphone light source can be transmitted to the shell light guide element, making the guide element emits light. The light guide structure of the earphone charging case use the light source of the earphone directly through optical simulation so as to realize secondary light guide, so that the shell of the charging case emits light, no additional light source is required, costs are reduced, the size of charging case can be effectively reduced, and miniaturization and lightweight can be realized.

Abstract: In some embodiments, a method is provided. The method includes identifying an incident situation based upon a sensor detecting an abnormal condition. One or more life safety systems are queried to obtain life safety system data. One or more databases, comprising equipment information, chemical information, personnel information, and/or emergency response contingency procedures, are queried to obtain on-site information. The life safety system data and the on-site information are integrated together to generate incident situation information. The incident situation information is displayed through an electronic display.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.