Abstract: A near-eye display device includes a camera module, a display module and a rotating module. The camera module is configured for obtaining an image information along a direction of a first optical axis. The display module is configured for transmitting an image light of virtual information to a human eye along a second optical axis. The rotating module is configured for controlling the rotation of the camera module to change a position of the first optical axis, so as to switch the near-eye display device between a state of close-up view and a state of distant view. In the state of distant view, an angle between the first optical axis and the second optical axis is 25°. In the state of close-up view, the angle between the first optical axis and the second optical axis is less than or equal to 13°.

Abstract: A processing method for automatically generating machining features is provided. A workpiece CAD file is obtained to perform a CAD numerical analysis on a blank body. With the workpiece CAD file being used as a target, a workpiece CAD appearance is compared with the blank body to obtain a feature identification result of a first to-be-processed blank body, which includes identifying data of a to-be-removed blank body and a feature of a first processing surface. A geometric analysis is performed on the first processing surface feature and a tool selection range is determined. A virtual cutting simulation is performed on the first processing surface to generate a processed area data and an unprocessed area data. A spatial coordinate mapping comparison between the unprocessed area data and a surface data of the workpiece CAD file is performed to obtain a feature identification result of a second to-be-processed blank body.

Abstract: A magnetic component includes a magnetic core and a first winding module. The magnetic core has two opposite openings and at least one magnetic column. The first winding module has a plurality of annular metal plates disposed around the at least one magnetic column. Each of the annular metal plates has an electrical connection end, an annular portion and a heat-dissipating end. The electrical connection end and the heat-dissipation end are located at the two opposite openings of the magnetic core respectively. A thermal-dissipating area of the heat-dissipating end is greater than a cross-sectional area of a connection portion between the heat-dissipating end and the annular portion.

Abstract: A high-bandwidth bend-insensitive multimode fiber includes a core laver and a cladding including an inner cladding, a depressed cladding, and an outer cladding arranged sequentially from inside to outside. The core layer is a silicon dioxide glass layer co-doped with germanium, phosphorus (P), and fluorine (F) and has a refractive index profile in a shape of a parabola, a distribution index in a range of 2.0-2.3, a radius in a range of 23-27 ?m, and a maximum relative refractive index difference in a range of 0.9-1.2% at its center. A contribution amount of P at the center is in a range of 0.01-0.30%. A doping amount of F increases from the center to the edge of the core layer. A contribution amount of F at the center and edge of the core layer is in range of 0.0% to ?0.1%, and ?0.40% to ?0.20%, respectively.

Abstract: A semiconductor device includes a source/drain portion, a metal silicide layer disposed over the source/drain portion, and a transition layer disposed between the source/drain portion and the metal silicide layer. The transition layer includes implantation elements, and an atomic concentration of the implantation elements in the transition layer is higher than that in each of the source/drain portion and the metal silicide layer so as to reduce a contact resistance between the source/drain portion and the metal silicide layer. Methods for manufacturing the semiconductor device are also disclosed.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a gate structure disposed on the fin structure, a source/drain (S/D) region disposed adjacent to the gate structure, a contact structure disposed on the S/D region, and a dipole layer disposed at an interface between the ternary compound layer and the S/D region. The contact structure includes a ternary compound layer disposed on the S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a gate structure disposed on the fin structure, a source/drain (S/D) region disposed adjacent to the gate structure, a contact structure disposed on the S/D region, and a dipole layer disposed at an interface between the ternary compound layer and the S/D region. The contact structure includes a ternary compound layer disposed on the S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.

Abstract: A display device and a manufacturing method thereof are provided. The display device includes a first liquid crystal panel for displaying a picture, a second liquid crystal panel for switching between a privacy mode and a sharing mode, and a back light assembly for emitting light; the second liquid crystal panel is disposed on a light-emitting side of the back light assembly; the first liquid crystal panel is disposed on a side of the second liquid crystal panel away from the back light assembly, and a spacer film is disposed between the first liquid crystal panel and the second liquid crystal panel, and is attached to the second liquid crystal panel.

Abstract: A semiconductor structure includes a semiconductor substrate, a first source/drain portion, a second source/drain portion, a first metal contact, a second metal contact and a first conductive carbon layer. The first and second source/drain portions are formed over the semiconductor substrate, and are spaced apart from each other. The first source/drain portion has a conductivity type different from that of the second source/drain portion. The first and second metal contacts are respectively formed on the first and second source/drain portions. The first conductive carbon layer is formed between the first source/drain portion and the first metal contact.

Abstract: The disclosure describes methods of treating humans with Duchenne muscular dystrophy by providing doses of an AAV9 vector that expresses a mini-dystrophin protein in transduced muscle cells.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

Abstract: An echo estimation system includes a transceiver circuitry and a processor circuitry. The processor circuitry is coupled to the transceiver circuitry. The processor circuitry is configured to calculate linear echo power and non-linear echo power based on a signal under test in the transceiver circuitry. The linear echo power and the non-linear echo power are utilized to determine a quality of the transceiver circuitry or utilized to determine component parameters of the transceiver circuitry.

Abstract: Provided are an information management system and method for a communication application, and a display terminal. The system includes a personal information display module and a posted information display module; the personal information display module is configured to display personal information of a poster; and the posted information display module is configured to dynamically display a plurality of posted contents contained in a moment posted by the poster at current time.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

Abstract: A feedback loop circuit of a voltage regulator includes a loadline and a compensation circuit. The loadline generates a feedback signal according to a sensed current signal that provides information of an inductor current of the voltage regulator, and outputs the feedback signal to a controller circuit of the voltage regulator for regulating an output voltage of the voltage regulator. The compensation circuit generates a compensation signal to compensate for a deviation of the output voltage, wherein the feedback signal generated from the loadline is affected by the compensation signal.

Abstract: A sub-circuit of a voltage regulator includes a load condition detection circuit and a controllable circuit. The load condition detection circuit is arranged to detect a load transient frequency of a load powered by the voltage regulator, and generate a control signal according to a detection result of the load transient frequency. The controllable circuit is arranged to receive the control signal, wherein an operational behavior of the controllable circuit dynamically changes in response to the control signal.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Abstract: A display device and a manufacturing method thereof are provided. The display device includes a first liquid crystal panel for displaying a picture, a second liquid crystal panel for switching between a privacy mode and a sharing mode, and a back light assembly for emitting light; the second liquid crystal panel is disposed on a light-emitting side of the back light assembly; the first liquid crystal panel is disposed on a side of the second liquid crystal panel away from the back light assembly, and a spacer film is disposed between the first liquid crystal panel and the second liquid crystal panel, and is attached to the second liquid crystal panel.