Abstract: A display device and a manufacturing method thereof are provided. The display device includes a first liquid crystal panel for displaying a picture, a second liquid crystal panel for switching between a privacy mode and a sharing mode, and a back light assembly for emitting light; the second liquid crystal panel is disposed on a light-emitting side of the back light assembly; the first liquid crystal panel is disposed on a side of the second liquid crystal panel away from the back light assembly, and a spacer film is disposed between the first liquid crystal panel and the second liquid crystal panel, and is attached to the second liquid crystal panel.

Abstract: A semiconductor structure includes a semiconductor substrate, a first source/drain portion, a second source/drain portion, a first metal contact, a second metal contact and a first conductive carbon layer. The first and second source/drain portions are formed over the semiconductor substrate, and are spaced apart from each other. The first source/drain portion has a conductivity type different from that of the second source/drain portion. The first and second metal contacts are respectively formed on the first and second source/drain portions. The first conductive carbon layer is formed between the first source/drain portion and the first metal contact.

Abstract: The disclosure describes methods of treating humans with Duchenne muscular dystrophy by providing doses of an AAV9 vector that expresses a mini-dystrophin protein in transduced muscle cells.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

Abstract: An echo estimation system includes a transceiver circuitry and a processor circuitry. The processor circuitry is coupled to the transceiver circuitry. The processor circuitry is configured to calculate linear echo power and non-linear echo power based on a signal under test in the transceiver circuitry. The linear echo power and the non-linear echo power are utilized to determine a quality of the transceiver circuitry or utilized to determine component parameters of the transceiver circuitry.

Abstract: Provided are an information management system and method for a communication application, and a display terminal. The system includes a personal information display module and a posted information display module; the personal information display module is configured to display personal information of a poster; and the posted information display module is configured to dynamically display a plurality of posted contents contained in a moment posted by the poster at current time.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

Abstract: A feedback loop circuit of a voltage regulator includes a loadline and a compensation circuit. The loadline generates a feedback signal according to a sensed current signal that provides information of an inductor current of the voltage regulator, and outputs the feedback signal to a controller circuit of the voltage regulator for regulating an output voltage of the voltage regulator. The compensation circuit generates a compensation signal to compensate for a deviation of the output voltage, wherein the feedback signal generated from the loadline is affected by the compensation signal.

Abstract: A sub-circuit of a voltage regulator includes a load condition detection circuit and a controllable circuit. The load condition detection circuit is arranged to detect a load transient frequency of a load powered by the voltage regulator, and generate a control signal according to a detection result of the load transient frequency. The controllable circuit is arranged to receive the control signal, wherein an operational behavior of the controllable circuit dynamically changes in response to the control signal.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Abstract: A display device and a manufacturing method thereof are provided. The display device includes a first liquid crystal panel for displaying a picture, a second liquid crystal panel for switching between a privacy mode and a sharing mode, and a back light assembly for emitting light; the second liquid crystal panel is disposed on a light-emitting side of the back light assembly; the first liquid crystal panel is disposed on a side of the second liquid crystal panel away from the back light assembly, and a spacer film is disposed between the first liquid crystal panel and the second liquid crystal panel, and is attached to the second liquid crystal panel.

Abstract: A system for determining the cause of an abnormality in a semiconductor manufacturing process includes an abnormality mode determination module, a selection module, and a root cause analysis module. The abnormality mode determination module is used to determine the similarity between wafer bin maps containing the abnormal data. When the similarity among the wafer maps is higher than a reference value, the selection module executes the steps of: determining a bad lot based on the wafer maps where the similarity is higher than the reference value; determining a time span within which the bad lot is generated; selecting other bad lots occurring in the time span and satisfying a failure model; selecting a good lot based on a fixed lot interval. The root cause analysis module is used to execute the steps of calculating the correlation among data to obtain confidence indexes.

Abstract: A processing method for automatically generating machining features is provided. A workpiece CAD file is obtained to perform a CAD numerical analysis on a blank body. With the workpiece CAD file being used as a target, a workpiece CAD appearance is compared with the blank body to obtain a feature identification result of a first to-be-processed blank body, which includes identifying data of a to-be-removed blank body and a feature of a first processing surface. A geometric analysis is performed on the first processing surface feature and a tool selection range is determined. A virtual cutting simulation is performed on the first processing surface to generate a processed area data and an unprocessed area data. A spatial coordinate mapping comparison between the unprocessed area data and a surface data of the workpiece CAD file is performed to obtain a feature identification result of a second to-be-processed blank body.

Abstract: An image calibration method for use in an imaging system. The imaging system includes a projection device, a color detector and a processor. The image calibration method includes in an ambient light environment, the color detector taking a background luminance and an ambient measurement of a test image on a projection surface, and the processor generating a color appearance representation using the background luminance and the ambient measurement, in a darkroom environment, the color detector taking a darkroom measurement of a test image, and if a surround ratio is less than a predetermined threshold, the processor generating a target using the darkroom measurement and the color appearance representation, and the processor configuring a gamut of the projection device according to the target, and adjusting an image according to the gamut and the darkroom measurement, and the projection device projecting the adjusted image.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a gate structure disposed on the fin structure, a source/drain (S/D) region disposed adjacent to the gate structure, a contact structure disposed on the S/D region, and a dipole layer disposed at an interface between the ternary compound layer and the S/D region. The contact structure includes a ternary compound layer disposed on the S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a first channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure.