Patents by Inventor Rong Tao
Rong Tao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11956207Abstract: An approach includes providing support multi-tenancy support on a DHCP protocol. The approach includes receiving a dynamic host configuration protocol (DHCP) packet, inserting a tenant-specific option information within the DHCP packet, and transmitting the DHCP packet with the tenant-specific option information.Type: GrantFiled: December 2, 2022Date of Patent: April 9, 2024Assignee: KYNDRYL, INC.Inventors: Liang Rong, Gang Tang, Zi J. Tao, Ming S. Xian
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Publication number: 20240108593Abstract: The disclosure provides a method of treating a polyamine imbalance-related disorder. The method comprises administering phenylbutyrate to a subject in need thereof, thereby treating the polyamine imbalance-related disorder.Type: ApplicationFiled: December 6, 2021Publication date: April 4, 2024Applicant: UNIVERSITY OF MIAMIInventors: Rong Grace Zhai, Xianzun Tao, Chong Li, Yi Zhu, Zoraida Diaz-Perez
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Patent number: 11948885Abstract: Methods and apparatus for creating a dual metal interconnect on a substrate. In some embodiments, a first liner of a first nitride material is deposited into at least one 1X feature and at least one wider than 1X feature, the first liner has a thickness of less than or equal to approximately 12 angstroms; a second liner of a first metal material is deposited into the at least one 1X feature and at least one wider than 1X feature; the first metal material is reflowed such that the at least one 1X feature is filled with the first metal material and the at least one wider than 1X feature remains unfilled with the first metal material; a second metal material is deposited on the first metal material, and the second metal material is reflowed such that the at least one wider than 1X feature is filled with the second metal material.Type: GrantFiled: June 24, 2021Date of Patent: April 2, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Suketu A. Parikh, Rong Tao, Roey Shaviv, Joung Joo Lee, Seshadri Ganguli, Shirish Pethe, David Gage, Jianshe Tang, Michael A Stolfi
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Publication number: 20220310363Abstract: Methods and apparatus for cleaning a process kit configured for processing a substrate are provided. For example, a process chamber for processing a substrate can include a chamber wall; a sputtering target disposed in an upper section of the inner volume; a pedestal including a substrate support having a support surface to support a substrate below the sputtering target; a power source configured to energize sputtering gas for forming a plasma in the inner volume; a process kit surrounding the sputtering target and the substrate support; and an ACT connected to the pedestal and a controller configured to tune the pedestal using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit, wherein the predetermined potential difference is based on a percentage of total capacitance of the ACT and a stray capacitance associated with a grounding path of the process chamber.Type: ApplicationFiled: June 13, 2022Publication date: September 29, 2022Inventors: Halbert CHONG, Rong TAO, Jianxin LEI, Rongjun WANG, Keith A. Miller, Irena H. Wysok, Tza-Jing Gung, Xing Chen
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Publication number: 20220310364Abstract: Methods and apparatus for cleaning a process kit configured for processing a substrate are provided. For example, a process chamber for processing a substrate can include a chamber wall; a sputtering target disposed in an upper section of the inner volume; a pedestal including a substrate support having a support surface to support a substrate below the sputtering target; a power source configured to energize sputtering gas for forming a plasma in the inner volume; a process kit surrounding the sputtering target and the substrate support; and an ACT connected to the pedestal and a controller configured to tune the pedestal using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit, wherein the predetermined potential difference is based on a percentage of total capacitance of the ACT and a stray capacitance associated with a grounding path of the process chamber.Type: ApplicationFiled: June 13, 2022Publication date: September 29, 2022Inventors: Halbert CHONG, Rong TAO, Jianxin LEI, Rongjun WANG, Keith A. Miller, Irena H. Wysok, Tza-Jing Gung, Xing Chen
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Publication number: 20220223472Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow material in features, e.g. vias, formed in a dielectric layer. A high melting point material is deposited in the feature and is reflowed and annealed in an ambient comprising one or more of hydrogen molecules, hydrogen ions, and hydrogen radicals at a temperature greater than 300° C. to fill the feature with a reflow material.Type: ApplicationFiled: January 11, 2021Publication date: July 14, 2022Applicant: Applied Materials, Inc.Inventors: Yi Luo, Rong Tao, Liqi Wu, Mingte Liu, Joung Joo Lee, Avgerinos V. Gelatos
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Publication number: 20210320064Abstract: Methods and apparatus for creating a dual metal interconnect on a substrate. In some embodiments, a first liner of a first nitride material is deposited into at least one 1X feature and at least one wider than 1X feature, the first liner has a thickness of less than or equal to approximately 12 angstroms; a second liner of a first metal material is deposited into the at least one 1X feature and at least one wider than 1X feature; the first metal material is reflowed such that the at least one 1X feature is filled with the first metal material and the at least one wider than 1X feature remains unfilled with the first metal material; a second metal material is deposited on the first metal material, and the second metal material is reflowed such that the at least one wider than 1X feature is filled with the second metal material.Type: ApplicationFiled: June 24, 2021Publication date: October 14, 2021Inventors: SUKETU A. PARIKH, RONG TAO, ROEY SHAVIV, JOUNG JOO LEE, SESHADRI GANGULI, SHIRISH PETHE, DAVID GAGE, JIANSHE TANG, MICHAEL A STOLFI
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Publication number: 20210319989Abstract: Methods and apparatus for cleaning a process kit configured for processing a substrate are provided. For example, a process chamber for processing a substrate can include a chamber wall; a sputtering target disposed in an upper section of the inner volume; a pedestal including a substrate support having a support surface to support a substrate below the sputtering target; a power source configured to energize sputtering gas for forming a plasma in the inner volume; a process kit surrounding the sputtering target and the substrate support; and an ACT connected to the pedestal and a controller configured to tune the pedestal using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit, wherein the predetermined potential difference is based on a percentage of total capacitance of the ACT and a stray capacitance associated with a grounding path of the process chamber.Type: ApplicationFiled: April 13, 2020Publication date: October 14, 2021Inventors: Halbert CHONG, Rong TAO, Jianxin LEI, Rongjun WANG, Keith A. Miller, Irena H. Wysok, Tza-Jing Gung, Xing Chen
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Patent number: 11075165Abstract: Methods and apparatus for creating a dual metal interconnect on a substrate. In some embodiments, a first liner of a first nitride material is deposited into at least one 1× feature and at least one wider than 1× feature, the first liner has a thickness of less than or equal to approximately 12 angstroms; a second liner of a first metal material is deposited into the at least one 1× feature and at least one wider than 1× feature; the first metal material is reflowed such that the at least one 1× feature is filled with the first metal material and the at least one wider than 1× feature remains unfilled with the first metal material; a second metal material is deposited on the first metal material, and the second metal material is reflowed such that the at least one wider than 1× feature is filled with the second metal material.Type: GrantFiled: July 19, 2019Date of Patent: July 27, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Suketu A Parikh, Rong Tao, Roey Shaviv, Joung Joo Lee, Seshadri Ganguli, Shirish Pethe, David Gage, Jianshe Tang, Michael A Stolfi
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Publication number: 20210020569Abstract: Methods and apparatus for creating a dual metal interconnect on a substrate. In some embodiments, a first liner of a first nitride material is deposited into at least one 1× feature and at least one wider than 1× feature, the first liner has a thickness of less than or equal to approximately 12 angstroms; a second liner of a first metal material is deposited into the at least one 1× feature and at least one wider than 1× feature; the first metal material is reflowed such that the at least one 1× feature is filled with the first metal material and the at least one wider than 1× feature remains unfilled with the first metal material; a second metal material is deposited on the first metal material, and the second metal material is reflowed such that the at least one wider than 1× feature is filled with the second metal material.Type: ApplicationFiled: July 19, 2019Publication date: January 21, 2021Inventors: SUKETU A. PARIKH, RONG TAO, ROEY SHAVIV, JOUNG JOO LEE, SESHADRI GANGULI, SHIRISH PETHE, DAVID GAGE, JIANSHE TANG, MICHAEL A. STOLFI
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Patent number: 10304732Abstract: Methods and apparatus for filling features with cobalt are provided herein. In some embodiments, a method for processing a substrate includes: depositing a first cobalt layer via a chemical vapor deposition (CVD) process atop a substrate and within a feature disposed in the substrate; and at least partially filling the feature with cobalt or cobalt containing material by performing a plasma process in a physical vapor deposition (PVD) chamber having a cobalt target to reflow a portion of the first cobalt layer into the feature. The PVD chamber may be configured to simultaneously deposit cobalt or cobalt containing material within the feature from a cobalt target disposed in the PVD chamber.Type: GrantFiled: September 21, 2017Date of Patent: May 28, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Wenting Hou, Jianxin Lei, Joung Joo Lee, Rong Tao
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Publication number: 20190088540Abstract: Methods and apparatus for filling features with cobalt are provided herein. In some embodiments, a method for processing a substrate includes: depositing a first cobalt layer via a chemical vapor deposition (CVD) process atop a substrate and within a feature disposed in the substrate; and at least partially filling the feature with cobalt or cobalt containing material by performing a plasma process in a physical vapor deposition (PVD) chamber having a cobalt target to reflow a portion of the first cobalt layer into the feature. The PVD chamber may be configured to simultaneously deposit cobalt or cobalt containing material within the feature from a cobalt target disposed in the PVD chamber.Type: ApplicationFiled: September 21, 2017Publication date: March 21, 2019Inventors: Wenting Hou, Jianxin Lei, Joung Joo Lee, Rong Tao
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Publication number: 20180327893Abstract: A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target.Type: ApplicationFiled: July 11, 2018Publication date: November 15, 2018Inventors: Peijun DING, Rong TAO, Zheng XU, Daniel C. LUBBEN, Suraj RENGARAJAN, Michael A. MILLER, Arvind SUNDARRAJAN, Xianmin TANG, John C. FORSTER, Jianming FU, Roderick C. MOSELY, Fusen CHEN, Praburam GOPALRAJA
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Patent number: 10047430Abstract: A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target.Type: GrantFiled: March 11, 2014Date of Patent: August 14, 2018Assignee: APPLIED MATERIALS, INC.Inventors: Peijun Ding, Rong Tao, Zheng Xu, Daniel C. Lubben, Suraj Rengarajan, Michael A. Miller, Arvind Sundarrajan, Xianmin Tang, John C. Forster, Jianming Fu, Roderick C. Mosely, Fusen Chen, Praburam Gopalraja
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Patent number: 10014179Abstract: Methods for processing a substrate include: (a) depositing a cobalt layer to a first thickness within a first plurality of features and a second plurality of features formed in a substrate, wherein each of the first plurality of features and each of the second plurality of features comprises an opening, and wherein a width of the openings of the first plurality of features is less than a width of the openings of the second plurality of features; and (b) heating the substrate to a first temperature to fill the first plurality of features with cobalt material while simultaneously depositing a fill material on the substrate to fill the second plurality of features.Type: GrantFiled: February 9, 2016Date of Patent: July 3, 2018Assignee: APPLIED MATERIALS, INC.Inventors: Rong Tao, Tae Hong Ha, Xianmin Tang, Joung Joo Lee
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Patent number: 9650512Abstract: A halogen-free resin composition, a copper clad laminate using the same, and a printed circuit board using the same are introduced. The halogen-free resin composition comprising (A) 100 parts by weight of epoxy resin; (B) 3 to 15 parts by weight of diaminodiphenyl sulfone (DDS); and (C) 5 to 70 parts by weight of phenolic co-hardener. The halogen-free resin composition features specific ingredients and proportion to thereby achieve satisfactory maximum preservation period of the prepreg manufactured from the halogen-free resin composition, control the related manufacturing process better, and attain satisfactory laminate properties, such as a high degree of water resistance, a high degree of heat resistance, and satisfactory dielectric properties, and thus is suitable for producing a prepreg or a resin film to thereby be applicable to copper clad laminates and printed circuit boards.Type: GrantFiled: August 10, 2013Date of Patent: May 16, 2017Assignee: Elite Electronic Material (Kunshan) Co., LtdInventors: Rong-Tao Wang, Li-Chih Yu, Yu-Te Lin, Yi-Jen Chen, Wenjun Tian, Ziqian Ma, Wenfeng Lu
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Publication number: 20160240432Abstract: Methods for processing a substrate include: (a) depositing a cobalt layer to a first thickness within a first plurality of features and a second plurality of features formed in a substrate, wherein each of the first plurality of features and each of the second plurality of features comprises an opening, and wherein a width of the openings of the first plurality of features is less than a width of the openings of the second plurality of features; and (b) heating the substrate to a first temperature to fill the first plurality of features with cobalt material while simultaneously depositing a fill material on the substrate to fill the second plurality of features.Type: ApplicationFiled: February 9, 2016Publication date: August 18, 2016Inventors: RONG TAO, TAE HONG HA, XIANMIN TANG, JOUNG JOO LEE
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Patent number: 9288904Abstract: A halogen-free resin composition includes (A) 100 parts by weight of epoxy resin; (B) 10 to 100 parts by weight of benzoxazine resin; (C) 5 to 50 parts by weight of diallylbisphenol A resin; and (D) 0.05 to 20 parts by weight of an amine curing agent. The halogen-free resin composition includes specific ingredients and proportions thereof to attain low dielectric constant (Dk), low dissipation factor (Df), high heat resistance, and high flame retardation. The halogen-free resin composition is suitable for producing a prepreg or a resin film and thus applicable to copper clad laminates and printed circuit boards.Type: GrantFiled: January 11, 2013Date of Patent: March 15, 2016Assignee: ELITE ELECTRONIC MATERIAL (KUNSHAN) CO., LTDInventors: Rong-Tao Wang, Li-Ming Chou, Li-Chih Yu, Yu-Te Lin
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Patent number: 9131607Abstract: A halogen-free resin composition includes (A) 100 parts by weight of naphthalene epoxy resin; (B) 10 to 100 parts by weight of styrene maleic anhydride copolymer; and (C) 30 to 70 parts by weight of DOPO-containing bisphenol F novolac resin. The halogen-free resin composition includes specific ingredients, and is characterized by specific proportions thereof, to thereby attain a low dielectric constant, a low dielectric dissipation factor, high heat resistance, and high flame retardation, and thus is suitable for producing a prepreg or a resin film to thereby be applicable to copper clad laminates and printed circuit boards.Type: GrantFiled: February 26, 2013Date of Patent: September 8, 2015Assignee: ELITE ELECTRONIC MATERIAL (KUNSHAN) CO., LTD.Inventors: Rong-Tao Wang, Tse-An Lee, Yi-Jen Chen, Wenjun Tian, Ziqian Ma, Wenfeng Lu
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Publication number: 20150136732Abstract: A method and apparatus for depositing films on a substrate is described. The method includes depositing a film on a substrate with feature formed therein or thereon. The feature includes a first surface and a second surface that are at different levels. A least a portion of the deposited film is removed by exposing the substrate to an ion flux from a linear ion source. The ion flux has an ion angular spread of less than or equal to 90 degrees and greater than or equal to 15 degrees. In certain embodiments, the feature can be a nanoscale, high aspect ratio feature such as narrow, deep trench, a small diameter, deep hole, or a dual damascene structure. Such features are often found in integrated circuit devices.Type: ApplicationFiled: November 19, 2014Publication date: May 21, 2015Inventors: Xianmin TANG, Ludovic GODET, Guojun LIU, Jing TANG, Phillip STOUT, Rong TAO