Patents by Inventor Rong Tao

Rong Tao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040035692
    Abstract: An array of auxiliary magnets is disclosed that is positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward the wafer. The auxiliary magnets may be either permanent magnets or electromagnets.
    Type: Application
    Filed: August 22, 2003
    Publication date: February 26, 2004
    Inventors: Peijun Ding, Rong Tao, Zheng Xu
  • Patent number: 6627542
    Abstract: A method and apparatus is provided for improving adherence of metal seed layers to barrier layers in electrochemical deposition techniques. The method includes depositing an adhesion layer continuously or semi-continuously without agglomeration onto a barrier layer prior to depositing a seed layer by controlling the substrate temperature, the chamber pressure, and/or the power delivered to a deposition chamber. Deposition of the adhesion layer prevents layer delamination which leads to agglomeration of the deposited layers and formation of voids in the high aspect ratio features.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: September 30, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Srinivas Gandikota, Rong Tao, Liang-Yuh Chen, Seshadri Ramaswami
  • Patent number: 6610184
    Abstract: An array of auxiliary magnets is disclosed that is positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward the wafer. The auxiliary magnets may be either permanent magnets or electromagnets.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: August 26, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Peijun Ding, Rong Tao, Zheng Xu
  • Publication number: 20030089601
    Abstract: An array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward the wafer. The auxiliary magnets may be either permanent magnets or electromagnets.
    Type: Application
    Filed: November 14, 2001
    Publication date: May 15, 2003
    Inventors: Peijun Ding, Rong Tao, Zheng Xu
  • Publication number: 20020144889
    Abstract: A burn-in process is performed in a high density plasma sputtering chamber to remove contaminants from a coil and a sputtering target installed in the chamber. The process includes applying respective power signals to the coil and to the sputtering target while maintaining a pressure level in the chamber that is lower than the conventional pressure level of 40 mT. Preferably the pressure level is maintained at substantially 10 mT.
    Type: Application
    Filed: April 9, 2001
    Publication date: October 10, 2002
    Applicant: Applied Materials, Inc.
    Inventors: Rong Tao, Peijun Ding
  • Patent number: 6207222
    Abstract: The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates a barrier layer deposited on all exposed surface of a dielectric layer which contains a dual damascene via and wire definition. A conductive metal is deposited on the barrier layer using two or more deposition methods to fill the via and wire definition prior to planarization. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.
    Type: Grant
    Filed: August 24, 1999
    Date of Patent: March 27, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Liang-Yuh Chen, Rong Tao, Ted Guo, Roderick Craig Mosely
  • Patent number: 6200433
    Abstract: The present invention generally provides a copper metallization method for depositing a conformal barrier layer and seed layer in a plasma chamber. The barrier layer and seed layer are preferably deposited in a plasma chamber having an inductive coil and a target comprising the material to be sputtered. One or more plasma gases having high molar masses relative to the target material are then introduced into the chamber to form a plasma. Preferably, the plasma gases are selected from xenon, krypton or a combination thereof.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: March 13, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Peijun Ding, Rong Tao, Barry Chin, Dan Carl
  • Patent number: 6139697
    Abstract: The present invention relates generally to an improved process for providing complete via fill on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer, such as CVD Al or CVD Cu, is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD Cu. Next, a PVD Cu is deposited onto the previously formed CVD Cu layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD Cu layer is substantially void-free.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: October 31, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Liang-Yuh Chen, Roderick Craig Mosely, Fusen Chen, Rong Tao, Ted Guo
  • Patent number: 5989623
    Abstract: The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates a barrier layer deposited on all exposed surface of a dielectric layer which contains a dual damascene via and wire definition. A conductive metal is deposited on the barrier layer using two or more deposition methods to fill the via and wire definition prior to planarization. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.
    Type: Grant
    Filed: August 19, 1997
    Date of Patent: November 23, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Liang-Yuh Chen, Rong Tao, Ted Guo, Roderick Craig Mosely