Patents by Inventor Roy Alan Hastings
Roy Alan Hastings has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11770118Abstract: In one embodiment, a system includes a power delivery (“PD”) controller in a USB Type-C system that includes a configuration channel (“CC”), PD preamble detector, and a power-usage circuit. The PD controller includes a CC input that receives a PD message. The PD preamble detector is configured to detect a PD message preamble based in part upon a power of a filtered PD message and communicates a wake-up signal to the power-usage circuit in response to detecting a PD message preamble. The power-usage circuit is configured to exit a low-power mode in response to receiving the wake-up signal.Type: GrantFiled: November 10, 2020Date of Patent: September 26, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Deric Wayne Waters, Roy Alan Hastings
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Patent number: 11719728Abstract: A sectioned field effect transistor (“FET”) for implementing a rapidly changing sense range ratio dynamically in response to changing load and main supply conditions. The sectioned FET may have multiple main FET sections, and multiple sense FET sections. These sections can be dynamically connected and disconnected from the sectioned FET. The sections may also be connected by a common gate. There may also be common drain or source connections for the main FET sections, and also common drain or source connections for the sense FET sections. The sectioned FET allows for the sense range to be extended by a multiple of k+1, where k is the size ratio or factor of the additional sense FET sections. This allows the current sense range ratio to be extended to (m+n)/n*(k+1).Type: GrantFiled: September 26, 2022Date of Patent: August 8, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Roy Alan Hastings
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Publication number: 20230019385Abstract: A sectioned field effect transistor (“FET”) for implementing a rapidly changing sense range ratio dynamically in response to changing load and main supply conditions. The sectioned FET may have multiple main FET sections, and multiple sense FET sections. These sections can be dynamically connected and disconnected from the sectioned FET. The sections may also be connected by a common gate. There may also be common drain or source connections for the main FET sections, and also common drain or source connections for the sense FET sections. The sectioned FET allows for the sense range to be extended by a multiple of k+1, where k is the size ratio or factor of the additional sense FET sections. This allows the current sense range ratio to be extended to (m+n)/n*(k+1).Type: ApplicationFiled: September 26, 2022Publication date: January 19, 2023Inventor: Roy Alan Hastings
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Publication number: 20230006666Abstract: In examples, a circuit comprises a first current source coupled to a voltage source node. The circuit comprises a resistor having a first resistor terminal and a second resistor terminal, where the first resistor terminal is coupled to the first current source. The circuit comprises a bipolar transistor having a base, a collector, and an emitter, with the base coupled to the first resistor terminal, the emitter coupled to the second resistor terminal, and the collector coupled to the voltage source node. The circuit comprises a second current source coupled to the emitter and the second resistor terminal, with the second current source coupled to a ground node. The circuit comprises a Schmitt trigger having an input coupled to the emitter, the second resistor terminal, and the second current source.Type: ApplicationFiled: June 30, 2021Publication date: January 5, 2023Inventors: Chengxi LIU, Roy Alan HASTINGS
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Patent number: 11486909Abstract: A sectioned field effect transistor (“FET”) for implementing a rapidly changing sense range ratio dynamically in response to changing load and main supply conditions. The sectioned FET may have multiple main FET sections, and multiple sense FET sections. These sections can be dynamically connected and disconnected from the sectioned FET. The sections may also be connected by a common gate. There may also be common drain or source connections for the main FET sections, and also common drain or source connections for the sense FET sections. The sectioned FET allows for the sense range to be extended by a multiple of k+1, where k is the size ratio or factor of the additional sense FET sections. This allows the current sense range ratio to be extended to (m+n)/n*(k+1).Type: GrantFiled: October 22, 2020Date of Patent: November 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Roy Alan Hastings
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Patent number: 11387734Abstract: Aspects of the disclosure provide for a circuit. In at least some examples, the circuit includes a high-side power transistor, a low-side power transistor, a first transistor, a second transistor, and a third transistor. The high-side transistor is adapted to couple between an input node and a switch node. The low-side transistor is coupled between the switch node and ground. The first transistor is adapted to couple between a first node and the switch node. The second transistor is coupled between the first node and an output node. The third transistor is coupled between the first node and ground.Type: GrantFiled: September 17, 2020Date of Patent: July 12, 2022Assignee: Texas Instruments IncorporatedInventors: Riazdeen Buhari, Roy Alan Hastings, Nghia Trong Tang
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Patent number: 11289245Abstract: In an example, a device comprises a first resistor coupled to a second resistor and to a trim resistor, the second resistor and the trim resistor coupled to a port configured to couple to a third resistor. The device also comprises a comparator having an inverting input coupled to a first node between the second resistor and the port and a non-inverting input coupled to a second node between the first resistor and the trim resistor. The device further includes a trim control circuit coupled to an output of the comparator and having an output coupled to the trim resistor, the trim control circuit configured to couple to multiple integrated trim resistors external to the device.Type: GrantFiled: June 24, 2020Date of Patent: March 29, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Roy Alan Hastings
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Patent number: 11239656Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for current sensing and current limiting. An example apparatus includes a first main transistor including a first main transistor gate terminal coupled between an output terminal and an intermediate node; a second main transistor including a second main transistor gate terminal coupled between the intermediate node and a ground terminal; a first amplifier including a first amplifier output coupled to the first main transistor gate terminal; a second amplifier including a second amplifier output coupled to the second main transistor gate terminal; and a third amplifier including a third amplifier inverting input coupled to the intermediate node, a third amplifier non-inverting input coupled to a sense transistor, and a third amplifier output coupled to a third gate terminal of a third transistor.Type: GrantFiled: July 19, 2019Date of Patent: February 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Roy Alan Hastings
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Publication number: 20210091668Abstract: Aspects of the disclosure provide for a circuit. In at least some examples, the circuit includes a high-side power transistor, a low-side power transistor, a first transistor, a second transistor, and a third transistor. The high-side transistor is adapted to couple between an input node and a switch node. The low-side transistor is coupled between the switch node and ground. The first transistor is adapted to couple between a first node and the switch node. The second transistor is coupled between the first node and an output node. The third transistor is coupled between the first node and ground.Type: ApplicationFiled: September 17, 2020Publication date: March 25, 2021Inventors: Riazdeen BUHARI, Roy Alan HASTINGS, Nghia Trong TANG
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Publication number: 20210055783Abstract: In one embodiment, a system includes a power delivery (“PD”) controller in a USB Type-C system that includes a configuration channel (“CC”), PD preamble detector, and a power-usage circuit. The PD controller includes a CC input that receives a PD message. The PD preamble detector is configured to detect a PD message preamble based in part upon a power of a filtered PD message and communicates a wake-up signal to the power-usage circuit in response to detecting a PD message preamble. The power-usage circuit is configured to exit a low-power mode in response to receiving the wake-up signal.Type: ApplicationFiled: November 10, 2020Publication date: February 25, 2021Inventors: Deric Wayne Waters, Roy Alan hastings
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Publication number: 20210041486Abstract: A sectioned field effect transistor (“FET”) for implementing a rapidly changing sense range ratio dynamically in response to changing load and main supply conditions. The sectioned FET may have multiple main FET sections, and multiple sense FET sections. These sections can be dynamically connected and disconnected from the sectioned FET. The sections may also be connected by a common gate. There may also be common drain or source connections for the main FET sections, and also common drain or source connections for the sense FET sections. The sectioned FET allows for the sense range to be extended by a multiple of k+1, where k is the size ratio or factor of the additional sense FET sections. This allows the current sense range ratio to be extended to (m+n)/n*(k+1).Type: ApplicationFiled: October 22, 2020Publication date: February 11, 2021Inventor: Roy Alan Hastings
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Publication number: 20210021122Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for current sensing and current limiting. An example apparatus includes a first main transistor including a first main transistor gate terminal coupled between an output terminal and an intermediate node; a second main transistor including a second main transistor gate terminal coupled between the intermediate node and a ground terminal; a first amplifier including a first amplifier output coupled to the first main transistor gate terminal; a second amplifier including a second amplifier output coupled to the second main transistor gate terminal; and a third amplifier including a third amplifier inverting input coupled to the intermediate node, a third amplifier non-inverting input coupled to a sense transistor, and a third amplifier output coupled to a third gate terminal of a third transistor.Type: ApplicationFiled: July 19, 2019Publication date: January 21, 2021Inventor: Roy Alan Hastings
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Patent number: 10866628Abstract: In one embodiment, a system includes a power delivery (“PD”) controller in a USB Type-C system that includes a configuration channel (“CC”), PD preamble detector, and a power-usage circuit. The PD controller includes a CC input that receives a PD message. The PD preamble detector is configured to detect a PD message preamble based in part upon a power of a filtered PD message and communicates a wake-up signal to the power-usage circuit in response to detecting a PD message preamble. The power-usage circuit is configured to exit a low-power mode in response to receiving the wake-up signal.Type: GrantFiled: April 10, 2018Date of Patent: December 15, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Deric Wayne Waters, Roy Alan Hastings
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Patent number: 10845396Abstract: A sectioned field effect transistor (“FET”) for implementing a rapidly changing sense range ratio dynamically in response to changing load and main supply conditions. The sectioned FET may have multiple main FET sections, and multiple sense FET sections. These sections can be dynamically connected and disconnected from the sectioned FET. The sections may also be connected by a common gate. There may also be common drain or source connections for the main FET sections, and also common drain or source connections for the sense FET sections. The sectioned FET allows for the sense range to be extended by a multiple of k+1, where k is the size ratio or factor of the additional sense FET sections. This allows the current sense range ratio to be extended to (m+n)/n*(k+1).Type: GrantFiled: September 19, 2018Date of Patent: November 24, 2020Assignee: Texas Instruments IncorporatedInventor: Roy Alan Hastings
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Publication number: 20200321149Abstract: In an example, a device comprises a first resistor coupled to a second resistor and to a trim resistor, the second resistor and the trim resistor coupled to a port configured to couple to a third resistor. The device also comprises a comparator having an inverting input coupled to a first node between the second resistor and the port and a non-inverting input coupled to a second node between the first resistor and the trim resistor. The device further includes a trim control circuit coupled to an output of the comparator and having an output coupled to the trim resistor, the trim control circuit configured to couple to multiple integrated trim resistors external to the device.Type: ApplicationFiled: June 24, 2020Publication date: October 8, 2020Inventor: Roy Alan Hastings
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Publication number: 20200273608Abstract: In an example, a device comprises a first resistor coupled to a second resistor and to a trim resistor, the second resistor and the trim resistor coupled to a port configured to couple to a third resistor. The device also comprises a comparator having an inverting input coupled to a first node between the second resistor and the port and a non-inverting input coupled to a second node between the first resistor and the trim resistor. The device further includes a trim control circuit coupled to an output of the comparator and having an output coupled to the trim resistor, the trim control circuit configured to couple to multiple integrated trim resistors external to the device.Type: ApplicationFiled: February 26, 2019Publication date: August 27, 2020Inventor: Roy Alan HASTINGS
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Patent number: 10734140Abstract: In an example, a device comprises a first resistor coupled to a second resistor and to a trim resistor, the second resistor and the trim resistor coupled to a port configured to couple to a third resistor. The device also comprises a comparator having an inverting input coupled to a first node between the second resistor and the port and a non-inverting input coupled to a second node between the first resistor and the trim resistor. The device further includes a trim control circuit coupled to an output of the comparator and having an output coupled to the trim resistor, the trim control circuit configured to couple to multiple integrated trim resistors external to the device.Type: GrantFiled: February 26, 2019Date of Patent: August 4, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Roy Alan Hastings
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Publication number: 20200088770Abstract: A sectioned field effect transistor (“FET”) for implementing a rapidly changing sense range ratio dynamically in response to changing load and main supply conditions. The sectioned FET may have multiple main FET sections, and multiple sense FET sections. These sections can be dynamically connected and disconnected from the sectioned FET. The sections may also be connected by a common gate. There may also be common drain or source connections for the main FET sections, and also common drain or source connections for the sense FET sections. The sectioned FET allows for the sense range to be extended by a multiple of k+1, where k is the size ratio or factor of the additional sense FET sections. This allows the current sense range ratio to be extended to (m+n)/n*(k+1).Type: ApplicationFiled: September 19, 2018Publication date: March 19, 2020Inventor: Roy Alan Hastings
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Patent number: 10574139Abstract: A reference signal generator includes a voltage reference, an amplifier coupled to the voltage reference, and a precharge circuit coupled to the amplifier. The voltage reference is configured to generate a constant voltage. The amplifier is configured to receive the constant voltage from the voltage reference and generate a regulating primary output signal and a non-regulating secondary output signal. The precharge circuit is configured to charge a noise reduction capacitor with the non-regulating secondary output signal.Type: GrantFiled: December 20, 2018Date of Patent: February 25, 2020Assignee: Texas Instruments IncorporatedInventor: Roy Alan Hastings
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Publication number: 20190310700Abstract: In one embodiment, a system includes a power delivery (“PD”) controller in a USB Type-C system that includes a configuration channel (“CC”), PD preamble detector, and a power-usage circuit. The PD controller includes a CC input that receives a PD message. The PD preamble detector is configured to detect a PD message preamble based in part upon a power of a filtered PD message and communicates a wake-up signal to the power-usage circuit in response to detecting a PD message preamble. The power-usage circuit is configured to exit a low-power mode in response to receiving the wake-up signal.Type: ApplicationFiled: April 10, 2018Publication date: October 10, 2019Inventors: Deric Wayne Waters, Roy Alan Hastings