Abstract: A structure and method of minimizing package-shift effects in integrated circuits is implemented by using a thick metallic overcoat applied after the deposition and patterning of the conventional insulating protective overcoat. The metallic overcoat most preferably comprises a layer of electrolytically deposited copper approximately 15 &mgr;m thick that is patterned to provide for electrically independent regions; but an unbroken area of the metallic overcoat is left over any sensitive analog circuitry, such as a bandgap reference circuit. The thick metallic coating, in addition to minimizing package-shift effects, is also useful as a low-resistance routing layer. The metallic overcoat is sufficiently thin to allow low-profile packaging. The method employs a conductive overcoat that is significantly thin compared to conventional insulating conformal overcoats.

Abstract: A structure and method of minimizing package-shift effects in integrated circuits is implemented by using a thick metallic overcoat applied after the deposition and patterning of the conventional insulating protective overcoat. The metallic overcoat most preferably comprises a layer of electrolytically deposited copper approximately 15 &mgr;m thick that is patterned to provide for electrically independent regions; but an unbroken area of the metallic overcoat is left over any sensitive analog circuitry, such as a bandgap reference circuit. The thick metallic coating, in addition to minimizing package-shift effects, is also useful as a low-resistance routing layer. The metallic overcoat is sufficiently thin to allow low-profile packaging. The method employs a conductive overcoat that is significantly thin compared to conventional insulating conformal overcoats.

Abstract: A micropower low-dropout regulator (LDO) (30) having a low dropout voltage and a compensating impedance for compensating base current errors. The new compensation technique involves placing a shunt capacitor (C2) at a counterphase input (node A) of a Brokaw transconductance cell incorporating a base current compensation resistor (R5). The resistor (R5) and capacitor (C2) provide a zero frequency that does not depend upon the attenuation ratio of the feedback divider. The counterphase compensation capacitor (C2)provides a low-frequency zero using a reasonably sized capacitor, and provides a pole-zero separation that does not depend upon the attenuator ratio, without additional current-consuming components.

Abstract: A PFC controller (FIG. 5) provides power factor correction and peak current limiting for a switch-mode power converter of any topology (buck, boost or buck-boost), without having to directly sense inductor current. The PFC control technique involves using a piecewise-polynomial analog computer (AC) to compute power transistor on-times in accordance with separate polynomial transfer functions for power-factor control and peak-current-linking using as inputs current representations of line input voltage (VLN), load output voltage (VLD), and long-term current demand (VCD). A conduction cycle is initiated by sensing when the rate of change in the inductor current reaches zero using an auxiliary winding on the current storage inductor (Wzd), and terminated after the computed on-time to implement either power-factor control or peak-current-limiting.