Patents by Inventor Ru Chang

Ru Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140124798
    Abstract: A light-emitting element includes: a light-emitting structure; a plurality of first contact portions separately on the light-emitting structure; and a plurality of reflective portions disposed separately among the plurality of first contact portions.
    Type: Application
    Filed: November 5, 2012
    Publication date: May 8, 2014
    Applicant: EPISTAR CORPORATION
    Inventors: Jhih-Sian Wang, Yao-Ru Chang, Yiwen Huang, Guo-Chin Liu
  • Patent number: 8525328
    Abstract: The disclosure relates to a power device package structure. By employing the metal substrate of the power device package structure serve as a bottom electrode of a capacitor, the capacitor is integrated into the power device package structure. A dielectric material layer and a upper metal layer sequentially disposed on the metal substrate.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: September 3, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Jiin-Shing Perng, Min-Lin Lee, Shinn-Juh Lai, Huey-Ru Chang
  • Publication number: 20130221542
    Abstract: A device includes a spacer, which includes a recess extending from a top surface of the spacer into the spacer, and a conductive feature including a first portion and a second portion continuously connected to the first portion. The first portion extends into the recess. The second portion is on the top surface of the spacer. A die is attached to the spacer, and a lower portion of the first die extends into the recess.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 29, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ru Chang, Chung-Kai Wang, Ming-Che Wu
  • Publication number: 20130033752
    Abstract: A diffraction-type 3D display element is arranged on an image output face of a 3D display device and comprises a first diffraction area and a second diffraction area. The first diffraction area has a plurality of first stepped gratings spaced apart from each other. The second diffraction area has a plurality of second stepped gratings spaced apart from each other. The second diffraction area is adjacent to the first diffraction area and is arranged symmetrically to the first diffraction area with a central line being the symmetric axis. The diffraction-type 3D display element of the invention diffracts the images output by the 3D display device and projects the diffracted images to two different viewing areas to provide 3D images for users.
    Type: Application
    Filed: August 4, 2011
    Publication date: February 7, 2013
    Inventors: Chien-Yue CHEN, Wen-Chen Hung, Yao-Ru Chang
  • Patent number: 8240057
    Abstract: A method of manufacturing a self-aligned stylus with high sphericity includes the steps of: forming a polymeric layer on a substrate; placing a sphere on the polymeric layer; softening the polymeric layer to make a portion of the sphere sink into the polymeric layer; forming a specific light absorbing layer on the polymeric layer; illuminating the sphere and the specific light absorbing layer with specific light such that the specific light is focused by the sphere to expose the polymeric layer to form an exposed portion and an unexposed portion; removing the specific light absorbing layer; and baking the polymeric layer and then removing the unexposed portion. A self-aligned stylus with high sphericity is also disclosed.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: August 14, 2012
    Assignee: National Taiwan University
    Inventors: Wen-Pin Shih, Yao-Chuan Tsai, Duo-Ru Chang, Li-Chi Tsao, Ming-Dao Wu, Po-Jen Shih
  • Patent number: 8237520
    Abstract: A capacitor device is provided. The capacitor device includes at least one capacitor. The capacitor device also includes a first capacitor and a first filter coupling the first capacitor and a conductive region, wherein the first capacitor has a first resonance frequency and the first filter is configured to operate at a first frequency band covering the first resonance frequency.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: August 7, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Huey-Ru Chang, Min-Lin Lee, Jiin-Shing Perng, Sheng-Che Hung, Shinn-Juh Lai
  • Publication number: 20120168839
    Abstract: The disclosure relates to a power device package structure. By employing the metal substrate of the power device package structure serve as a bottom electrode of a capacitor, the capacitor is integrated into the power device package structure. A dielectric material layer and a upper metal layer sequentially disposed on the metal substrate.
    Type: Application
    Filed: July 14, 2011
    Publication date: July 5, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jiin-Shing Perng, Min-Lin Lee, Shinn-Juh Lai, Huey-Ru Chang
  • Patent number: 8198538
    Abstract: A capacitive device is provided. The capacitive device includes a first electrode and a second electrode below the first electrode and spaced apart from the first electrode, wherein at least one of the first electrode and the second electrode includes a plurality of conductive step sections, the plurality of conductive step sections having different heights. The capacitive device also includes an insulating region between the first electrode and the second electrode; and at least one slot formed on one of the first electrode and the second electrode.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: June 12, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Min Hsu, Min-Lin Lee, Shinn-Juh Lai, Huey-Ru Chang, Ray-Fong Hong
  • Patent number: 8053904
    Abstract: A semiconductor chip package structure for achieving flip-chip electrical connection without using a wire-bonding process includes a package unit, a semiconductor chip, a first insulative layer, first conductive layers, a second insulative layer, and second conductive layers. The package unit has a receiving groove. The semiconductor chip is received in the receiving groove and has a plurality of conductive pads disposed on its top surface. The first insulative layer is formed between the conductive pads to insulate the conductive pads. The first conductive layers are formed on the first insulative layer and the package unit, and one side of each first conductive layer is electrically connected to the corresponding conductive pad. The second insulative layer is formed between the first conductive layers in order to insulate the first conductive layers from each other. The second conductive layers are respectively formed on the other opposite sides of the first conductive layers.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: November 8, 2011
    Assignee: Harvatek Corporation
    Inventors: Bily Wang, Hung-Chou Yang, Jeng-Ru Chang
  • Patent number: 8056058
    Abstract: The method for generating test cases for a software program includes the step of setting a plurality of reference points in accordance with a sentence of the software program. The tracing pairs each including an initial test case as well as its adjacent vertex are set if one of them is among the reference points and the other one is not among the reference points. The essential test cases are chosen from the tracing pairs.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: November 8, 2011
    Assignee: National Tsing Hua University
    Inventors: Chin Yu Huang, Jun Ru Chang, Chih Tung Hsu
  • Publication number: 20110229991
    Abstract: A semiconductor chip package structure for achieving flip-chip electrical connection without using a wire-bonding process includes a package unit, a semiconductor chip, a first insulative layer, first conductive layers, a second insulative layer, and second conductive layers. The package unit has a receiving groove. The semiconductor chip is received in the receiving groove and has a plurality of conductive pads disposed on its top surface. The first insulative layer is formed between the conductive pads to insulate the conductive pads. The first conductive layers are formed on the first insulative layer and the package unit, and one side of each first conductive layer is electrically connected to the corresponding conductive pad. The second insulative layer is formed between the first conductive layers in order to insulate the first conductive layers from each other. The second conductive layers are respectively formed on the other opposite sides of the first conductive layers.
    Type: Application
    Filed: June 1, 2011
    Publication date: September 22, 2011
    Applicant: HARVATEK CORPORATION
    Inventors: BILY WANG, HUNG-CHOU YANG, JENG-RU CHANG
  • Patent number: 7942341
    Abstract: A two dimensional dot code includes boundary dots, a direction dot and a code dot to regenerate an information therefrom. To decode the two dimensional dot code, the boundary dots and the direction dot are used to define coordinates of virtual code dots first and then, the code dot is compared with the coordinates of the virtual code dots. Thus, in order to retrieve the information represented by the two dimensional dot code, the position of the code dot can be rapidly determined without rotational correction of the image taken from the two dimensional dot code.
    Type: Grant
    Filed: July 4, 2008
    Date of Patent: May 17, 2011
    Assignee: Elan Microelectronics Corporation
    Inventors: Chen-Hua Ao, Yi-Hsin Tao, Cheng-Ru Chang
  • Publication number: 20110018018
    Abstract: A semiconductor chip package structure for achieving electrical connection without using wire-bonding process includes an insulative substrate unit, a package unit, a semiconductor chip, a first conductive unit, an insulative unit and a second conductive unit. The package unit is disposed on the insulative substrate unit to form a receiving groove. The semiconductor chip is received in the receiving groove. The semiconductor chip has a plurality of conductive pads. The first conductive unit has a plurality of first conductive layers formed on the package body, and one side of each first conductive layer is electrically connected to each conductive pad. The insulative unit has an insulative layer formed between the first conductive layers in order to insulate the first conductive layers from each other. The second conductive unit has a plurality of second conductive layers respectively formed on another sides of the first conductive layers.
    Type: Application
    Filed: December 29, 2009
    Publication date: January 27, 2011
    Applicant: HARVATEK CORPORATION
    Inventors: BILY WANG, HUNG-CHOU YANG, JENG-RU CHANG
  • Publication number: 20110018019
    Abstract: A semiconductor chip package structure for achieving flip-chip electrical connection without using a wire-bonding process includes a package unit, a semiconductor chip, a first insulative layer, first conductive layers, a second insulative layer, and second conductive layers. The package unit has a receiving groove. The semiconductor chip is received in the receiving groove and has a plurality of conductive pads disposed on its top surface. The first insulative layer is formed between the conductive pads to insulate the conductive pads. The first conductive layers are formed on the first insulative layer and the package unit, and one side of each first conductive layer is electrically connected to the corresponding conductive pad. The second insulative layer is formed between the first conductive layers in order to insulate the first conductive layers from each other. The second conductive layers are respectively formed on the other opposite sides of the first conductive layers.
    Type: Application
    Filed: December 29, 2009
    Publication date: January 27, 2011
    Applicant: HARVATEK CORPORATION
    Inventors: BILY WANG, HUNG-CHOU YANG, JENG-RU CHANG
  • Patent number: 7875808
    Abstract: An embedded capacitor device within a circuit board having an integrated circuitry thereon is provided. The circuit board has a common coupling area under the integrated circuitry. The embedded capacitor device includes a first capacitor section providing at least one capacitor to a first terminal set of the integrated circuitry and a second capacitor section providing at least one capacitor to a second terminal set of the integrated circuitry. A portion of the first capacitor section is in the common coupling area and has its coupling to the first terminal set located in the common coupling area. Similarly, a portion of the second capacitor section is in the common coupling area and has its coupling to the second terminal set located in the common coupling area.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: January 25, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Huey-Ru Chang, Min-Lin Lee, Shinn-Juh Lay, Chin Sun Shyu
  • Publication number: 20100128997
    Abstract: A code pattern for providing information is disclosed, which can effectively improve the ratio of effective marks, and the effective marks are distributed in a rhombus area. The code pattern comprises: a plurality of nominal positions and a plurality of information marks. The nominal positions are respectively located at a plurality of intersections of a plurality of first hypothetical lines and a plurality of second hypothetical lines, and the first hypothetical lines are parallel to one diagonal line within the rhombus area. The plurality of information marks are respectively disposed within the area formed by the nominal positions, and each information mark is used to represent one of at least two values.
    Type: Application
    Filed: March 27, 2009
    Publication date: May 27, 2010
    Applicant: ELAN MICROELECTRONICS CORP.
    Inventors: Cheng-Ru Chang, Wei-Kuo Mai
  • Publication number: 20100102134
    Abstract: A plurality of code patterns including at least two code patterns is provided. The code patterns represent identical information. Adjacent ones of the code patterns of the code patterns meet at an angle. The code patterns at least reduce visual impact.
    Type: Application
    Filed: January 8, 2009
    Publication date: April 29, 2010
    Applicant: ELAN MICROELECTRONICS CORP.
    Inventors: Cheng-Ru Chang, Wei-Kuo Mai
  • Publication number: 20090302114
    Abstract: A two dimensional dot code includes boundary dots, a direction dot and a code dot to regenerate an information therefrom. To decode the two dimensional dot code, the boundary dots and the direction dot are used to define coordinates of virtual code dots first and then, the code dot is compared with the coordinates of the virtual code dots. Thus, in order to retrieve the information represented by the two dimensional dot code, the position of the code dot can be rapidly determined without rotational correction of the image taken from the two dimensional dot code.
    Type: Application
    Filed: July 4, 2008
    Publication date: December 10, 2009
    Applicant: ELAN MICROELECTRONICS CORPORATION
    Inventors: CHEN-HUA AO, YI-HSIN TAO, CHENG-RU CHANG
  • Publication number: 20090267704
    Abstract: A capacitor device is provided. The capacitor device includes at least one capacitor. The capacitor device also includes a first capacitor and a first filter coupling the first capacitor and a conductive region, wherein the first capacitor has a first resonance frequency and the first filter is configured to operate at a first frequency band covering the first resonance frequency.
    Type: Application
    Filed: February 27, 2009
    Publication date: October 29, 2009
    Inventors: Huey-Ru CHANG, Min-Lin Lee, Jiin-Shing Perng, Sheng-Che Hung, Shinn-Juh Lai
  • Publication number: 20090219668
    Abstract: A capacitive device is provided. The capacitive device includes a first electrode and a second electrode below the first electrode and spaced apart from the first electrode, wherein at least one of the first electrode and the second electrode includes a plurality of conductive step sections, the plurality of conductive step sections having different heights. The capacitive device also includes an insulating region between the first electrode and the second electrode; and at least one slot formed on one of the first electrode and the second electrode.
    Type: Application
    Filed: February 25, 2009
    Publication date: September 3, 2009
    Inventors: Chien-Min Hsu, Min-Lin Lee, Shinn-Juh Lai, Huey-Ru Chang, Ray-Fong Hong