Abstract: A light emitting diode (LED) package includes at least one light emitting unit having a first electrode and a second electrode, a first molding compound covering a part of the light emitting unit to expose the first electrode and the second electrode, and a first light transmissive plate disposed on the first molding compound opposite the light emitting unit. A side surface of the first molding compound and a side surface of the first light transmissive plate are coplanar or have even adjoined edges.

Abstract: Disclosed is a resistive random access memory, comprising a substrate, an insulating layer, a bottom electrode, a resistive material film, and a top electrode in an order from bottom to top, wherein the resistive material film is a four-layer structure composed of a same metal oxide; and the four layers in the four-layer structure from bottom to top have resistance values which are increased one after another by more than 10 times, oxygen concentrations which are increased one after another and thickness which are decreased one after another. The present invention may achieve complete formation-rupture of oxygen vacancy conductive filaments (CF) in each layer by dividing the resistive material film of the same metal oxide into four layers according to the different oxygen concentrations, so as to control accurately the resistance values, so that 2-bit storage with high uniformity is achieved.

Abstract: The present invention discloses a short-gate tunneling field effect transistor having a non-uniformly doped vertical channel and a fabrication method thereof. The short-gate tunneling field effect transistor has a vertical channel and the channel region is doped in such a slowly-varied and non-uniform manner that a doping concentration in the channel region appears as a Gaussian distribution along a vertical direction and the doping concentration in the channel near the drain region is higher while the doping concentration in the channel near the source region is lower; and double control gates are formed at both sides of the vertical channel and the control gates form an L-shaped short-gate structure, so that a gate underlapped region is formed in the channel near the drain region, and a gate overlapped region is formed at the source region.

Abstract: The present invention discloses a radiation-hardened-by-design (RHBD) multi-gate device and a fabrication method thereof. The multi-gate device of the present invention includes a substrate; a source region and a drain region, which are on the substrate; a protruding fin structure and a field dielectric layer between the source region and the drain region on the substrate; a gate dielectric and a gate electrode on the fin structure and the dielectric layer; and two isolation layers separated to each other, which are disposed in the drain region between the adjacent two fins, wherein an interlayer is sandwiched between the two isolation layers.

Abstract: The present invention discloses a method for integrating a vertical nanowire transistor and belongs to a field of field effect transistor logic device in a CMOS ultra-large scale integrated circuit (ULSI). The method realizes the integration of the vertical-nanowire transistor by combining selective epitaxy and replacement gate on sidewall. In comparison with an existing method for forming a vertical nanowire channel by etching, a size and shape of a cross section of a device channel can be accurately controlled, a consistency of device characteristic can be improved, and an etching damage during the forming of a channel in the existing method can be avoided, thereby the device performance can be improved.

Abstract: The invention provides an LED including a first-type semiconductor layer, an emitting layer, a second-type semiconductor layer, a first electrode, a second electrode, a Bragg reflector structure, a conductive layer and insulation patterns. The first electrode and the second electrode are located on the same side of the Bragg reflector structure. The conductive layer is disposed between the Bragg reflector structure and the second-type semiconductor layer. The insulation patterns are disposed between the conductive layer and the second-type semiconductor layer. Each insulating layer has a first surface facing toward the second-type semiconductor layer, a second surface facing away from the second-type semiconductor layer, and an inclined surface. The inclined surface connects the first surface and the second surface and is inclined with respect to the first surface and the second surface.

Abstract: The present invention discloses a tunneling field effect transistor having a three-side source and a fabrication method thereof, referring to field effect transistor logic devices and circuits in CMOS ultra large scale integrated circuits (ULSI). By means of the strong depletion effect of the three-side source, the transistor can equivalently achieve a steep doping concentration gradient for the source junction, significantly optimizing the sub-threshold slope of the TFET. Meanwhile, the turn-on current of the transistor is boosted. Furthermore, due to a region uncovered by the gate between the gate and the drain, the bipolar conduction effect of the transistor is effectively inhibited, and on the other hand, in the small-size transistor a parasitic tunneling current at the corner of the source junction is inhibited. The fabrication method is simple and can be accurately controlled.

Abstract: The present invention discloses a preparation method of a germanium-based Schottky junction, comprising, cleaning a surface of N-type germanium-based substrate, then depositing a layer of CeO2 on the surface, and further depositing a layer of metal. The stability Ce—O—Ge bonds can be formed at the interface after rare earth oxides CeO2 are in contact with the germanium substrate, and this is beneficial to reduce the interface state density, improve the quality of the interface, and reduce the MIGS and suppress Fermi-level pinning. Meanwhile, the tunneling resistance introduced by CeO2 between the metal and the germanium substrate is smaller relative to the case of Si3N4, Al2O3, Ge3N4 or the like. In view of the excellent surface characteristics and small conduction band offset relative to the germanium substrate, interposing of the CeO2 dielectric layer is applicable to the preparation the germanium-based Schottky junction having a low resistivity.

Abstract: Disclosed herein is a method for fabricating a FinFET with separated double gates on a bulk silicon, comprising: forming a pattern for a source, a drain and a thin bar connecting the source and the drain; forming an oxidation isolation layer; forming a gate structure and a source/drain structure; and forming a metal contact and a metal interconnection. By means of the method herein, it is very easy to fabricate the FinFET with separated double gates on the bulk silicon wafer, and the overall process flow is completely compatible with the conventional silicon-based very large scale integrated circuit manufacturing technology. Thus, the method herein is simple, convenient and has a short process period, greatly economizing the cost of the silicon wafer. In addition, by employing the FinFET with separated double gates fabricated by the method according to the invention, the short channel effect can be effectively suppressed.

Abstract: A light-emitting device and a light-emitting module using the same are provided. The light-emitting device includes a substrate module and a light-emitting component. The substrate module includes a substrate, a first conductive layer, an insulation layer and a second conductive layer. The substrate has an upper surface. The insulation layer is formed on the upper surface of the substrate, separates the substrate and the first conductive layer and has an opening. The second conductive layer connects to the upper surface of the substrate and is separated from the first conductive layer. The light-emitting component is disposed on the substrate module and electrically connected to the first conductive layer and the second conductive layer.

Abstract: A flip chip light emitting diode package structure includes a package carrier, a light guiding unit and at least one light emitting unit. The light guiding unit and the light emitting unit are disposed on the package carrier, and the light emitting unit is located between the light guiding unit and the package carrier. A horizontal projection area of the light guiding unit is greater than that of the light emitting unit. The light emitting unit is adapted to emit a light beam, and the light beam enters the light guiding unit and emits from an upper surface of the light guiding unit away from the light emitting unit.

Abstract: A light emitting component includes a light emitting unit, a molding compound and a wavelength converting layer. The light emitting unit has a forward light emitting surface. The molding compound covers the light emitting unit. The wavelength converting layer is disposed above the molding compound. The wavelength converting layer has a first surface and a second surface opposite to the first surface, wherein the first surface is located between the forward light emitting surface and the second surface, and at least one of the first and second surfaces is non-planar.

Abstract: The present invention discloses a method for preparing a nano-scale field-effect transistor, and belongs to the field of large-scale integrated circuit manufacturing technologies. The method focuses on preparing a nano-scale field-effect transistor on an SOI substrate by epitaxial growth. In the invention, the material and appearance of a channel of a nano-scale device may be accurately controlled by using an epitaxy process, and the device performance may be further optimized; moreover, a threshold voltage may be flexibly adjusted to adapt for requirements of different IC designs by realizing different channel doping types and doping concentrations; also, a gate structure with a consistent width in a height direction may be obtained, the parasitism and fluctuation of the device may be reduced, and at the same time, the method can be well compatible with CMOS post-gate processes, and is simple in procedure and low in cost.

Abstract: A light emitting device including a circuit board, a light emitting unit, and an anisotropic conductive layer is provided. The circuit board includes a plurality of electrode pads. The light emitting unit includes a semiconductor epitaxial structure layer, a first electrode, and a second electrode. The first electrode and the second electrode are respectively disposed on the same side of the semiconductor epitaxial structure layer. The first electrode and the second electrode are electrically connected to the electrode pads through the anisotropic conductive layer. A fabricating method of a light emitting device is also provided.

Abstract: A semiconductor light emitting structure includes an epitaxial structure, an N-type electrode pad, a P-type electrode pad and an insulation layer. The N-type electrode pad and the P-type electrode pad are disposed on the epitaxial structure apart, wherein the P-type electrode pad has a first upper surface. The insulation layer is disposed on the epitaxial structure and located between the N-type electrode pad and the P-type electrode pad, wherein the insulation layer has a second upper surface. The first upper surface of the P-type electrode pad and the second upper surface of the insulation layer are coplanar.

Abstract: The present invention discloses an organic resistive random access memory and a preparation method thereof. The memory uses silicon as a substrate, and has a MIM capacitor structure having a vertical memory unit, where the MIM structure has a top electrode of Al, a bottom electrode of ITO, and an middle functional layer of parylene, wherein, a parylene layer as the functional layer is formed by performing deposition multiple times, where the deposition of Al2O3 is performed once by ALD between each two deposition of parylene. A critical region which is in favor of forming a conductive channel could be formed by controlling the deposition area of Al2O3, and further control the electrical characteristics of the memory. Through the present invention, the cycle-to-cycle and device-to-device uniformity could be effectively improved, without changing the basic structure of the memory.

Abstract: The disclosure relates to a high-voltage light-emitting diode (HV LED) and a manufacturing method thereof. A plurality of LED dies connected in series, in parallel, or in series and parallel are formed on a substrate. A side surface of the first semiconductor layer of part of the LED dies is aligned with a side surface of the substrate, such that no space for exposing the substrate is reserved between the LED dies and the edges of the substrate, the ratio of the substrate being covered by the LED dies is increased, that is, light-emitting area per unit area is increased, and the efficiency of light extraction of HV LED is improved.

Abstract: The present invention discloses a method for fabricating a quasi SOI source-drain multi-gate device, belonging to a field of manufacturing ultra large scale integrated circuit, the method comprises in sequence the following steps of: forming a Fin strip-shaped active region on a first semiconductor substrate; forming a STI isolation layer; depositing a gate dielectric layer and a gate material layer, forming a gate stack structure; forming a doped structure of a source-drain extension region; forming a recessed source-drain structure; forming a quasi SOI source-drain isolation layer; in-situ doping an epitaxial source and drain of a second semiconductor material and performing annealing for activating; removing a dummy gate and performing a deposition of a high k metal gate again; and forming a contact and a metal interconnection.

Abstract: A light emitting diode including a first-type semiconductor layer, an emitting layer, a second-type semiconductor layer, a first electrode, a second electrode, and a Bragg reflector structure. The emitting layer is configured to emit a light beam and is located between the first-type semiconductor layer and the second-type semiconductor layer. The light beam has a peak wavelength in a light emitting wavelength range. The first-type semiconductor layer, the emitting layer, and the second-type semiconductor layer are located on a same side of the Bragg reflector structure. A reflectance of the Bragg reflector structure is greater than or equal to 95% in a reflective wavelength range at least covering 0.8X nm to 1.8X nm, and X is the peak wavelength of the light emitting wavelength range.

Abstract: A method for fabricating multiple layers of ultra narrow silicon wires comprises the steps of fabricating wet-etch masking layers of silicon; forming a Fin and source/drain regions located at both ends thereof by epitaxy; forming the multiple layers of ultra narrow silicon wires. The present invention has advantages in that: the atom layer depositing may define the position of the ultra narrow silicon wires accurately, having a good controllability; the anisotropic wet-etch for silicon is performed in a self-stop manner and has a large process window, so that the cross-section shape of the nanowires formed by wet-etch is uniform and smooth.