Abstract: Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-signal modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.

Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider, a track-and-hold charge pump, and a frequency tracking circuit. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to divide the output clock to provide a feedback signal. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The frequency tracking circuit is configured to decrease frequency error between the feedback signal and the reference clock. The track-and-hold charge pump includes a pumping switch and a pulse width modulator (PWM). The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the feedback signal.

Abstract: A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period; a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.

Abstract: A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to a delay chain of the ring oscillator. The second and third transistors form a pseudo pass-gate inverter. An input of the pseudo pass-gate inverter is configured to receive an output signal of the delay chain. The first and fourth transistors are controlled by a realignment signal. When the realignment signal is in a realignment state, the first transistor is turned off and the fourth transistor is turned on, and when the realignment signal is in a normal state, the first transistor is turned on and the fourth transistor is turned off.

Abstract: Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-sigma modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.

Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operational mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operational mode of the hybrid PLL.

Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (??) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ?? TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ?? TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ?? TDC, wherein the MASH type high-order ?? TDC is configured to measure the phase noise of a device under text (DUT).

Abstract: A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to a delay chain of the ring oscillator. The second and third transistors form a pseudo pass-gate inverter. An input of the pseudo pass-gate inverter is configured to receive an output signal of the delay chain. The first and fourth transistors are controlled by a realignment signal. When the realignment signal is in a realignment state, the first transistor is turned off and the fourth transistor is turned on, and when the realignment signal is in a normal state, the first transistor is turned on and the fourth transistor is turned off.

Abstract: A frequency divider circuit includes a counter configured to generate a counter signal responsive to a frequency of a clock signal and a frequency ratio, and a compensation circuit coupled to the counter, and configured to generate an output signal. The output signal has a frequency equal to the frequency of the clock signal divided by a frequency ratio, and a duty cycle greater than 1/r, where r is the frequency ratio.

Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider, a track-and-hold charge pump, and a frequency tracking circuit. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to divide the output clock to provide a feedback signal. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The frequency tracking circuit is configured to decrease frequency error between the feedback signal and the reference clock. The track-and-hold charge pump includes a pumping switch and a pulse width modulator (PWM). The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the feedback signal.

Abstract: A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period; a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.

Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operational mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operational mode of the hybrid PLL.

Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.

Abstract: Track-and-hold charge pumps and PLL are provided. A track-and-hold charge pump includes a track-and-hold circuit, a transconductance amplifier, a pulse width modulator (PWM), and a pumping switch coupled to the transconductance amplifier. The track-and-hold circuit samples an input signal according to a reference clock. The transconductance amplifier converts the sampled input signal into a current. The PWM provides a PWM signal according to the reference clock. The pumping switch is controlled by the PWM signal, to provide an output current according to the current.

Abstract: A ring oscillator is provided. The ring oscillator includes a pseudo pass-gate inverter, a third transistor, a fourth transistor and a delay chain. The pseudo pass-gate inverter includes a first transistor and a second transistor in series. The third transistor is connected in series with the pseudo pass-gate inverter. The drain of the fourth transistor is connected to an output of the pseudo pass-gate inverter. The gate of the fourth transistor is connected to the gate of the third transistor to receive the realignment signal. The delay chain includes a plurality of delay cells. An input of the delay chain is connected to the output of the pseudo pass-gate inverter. When the realignment signal is in a realignment state, the third transistor is turned off, the fourth transistor is turned on.

Abstract: A realignment ring-cell circuit is disclosed. The circuit includes a single-to-differential unit, an OR gate, an AND gate, a first P-type metal-oxide-semiconductor transistor, and a first N-type metal-oxide-semiconductor transistor. The single-to-differential unit has an input configured to receive a realignment signal, a first output for outputting a first differential output and a second output for outputting a second differential output. The first output for outputting is a first input to the OR gate. The second output for outputting is a first input to the AND gate. A gate of the P-type metal-oxide-semiconductor transistor is electrically connected to an output of the OR gate. A gate of the N-type metal-oxide-semiconductor transistor is electrically connected to an output of the AND gate.

Abstract: A phase-locked loop circuit is disclosed. The circuit includes a digital bang-bang phase-locked loop (PLL) electrically connected to an input clock signal connection and an output clock signal connection, and a down-sampling circuit connected to the input clock signal connection. The circuit also includes a digitally-controlled delay line receiving an output of the down-sampling circuit, and an injection pulser receiving an output of the digitally-controlled delay line and connected to provide an injection pulse to a portion of the digital bang-bang phase-locked loop (PLL). The circuit further includes an injection timing calibration circuit connected to a control input of the digitally-controlled delay line. The circuit provides calibration of injection timing and bandwidth optimization, thereby reducing jitter in an output signal from the PLL.

Abstract: A realignment ring-cell circuit is disclosed. The circuit includes a single-to-differential unit, an OR gate, an AND gate, a first P-type metal-oxide-semiconductor transistor, and a first N-type metal-oxide-semiconductor transistor. The single-to-differential unit has an input configured to receive a realignment signal, a first output for outputting a first differential output and a second output for outputting a second differential output. The first output for outputting is a first input to the OR gate. The second output for outputting is a first input to the AND gate. A gate of the P-type metal-oxide-semiconductor transistor is electrically connected to an output of the OR gate. A gate of the N-type metal-oxide-semiconductor transistor is electrically connected to an output of the AND gate.

Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.

Abstract: A flicker noise measurement circuit includes a first section. The first section includes a plurality of first stages connected in series. The first section includes a first feedback switching element configured to selectively feedback an output of the plurality of first stages to an input of the plurality of first stages. The first section includes a first section connection switching element. The flicker noise measurement circuit includes a second section connected to the first section. The second section includes a plurality of second stages connected in series, wherein the first section connection switching element is configured to selectively connect the plurality of second stages to the plurality of first stages. The second section includes a second feedback switching element configured to selectively feedback an output of the plurality of second stages to the input of the plurality of first stages.