Patents by Inventor Ruey-Bin Sheen

Ruey-Bin Sheen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190058480
    Abstract: A phase-locked loop circuit is disclosed. The circuit includes a digital bang-bang phase-locked loop (PLL) electrically connected to an input clock signal connection and an output clock signal connection, and a down-sampling circuit connected to the input clock signal connection. The circuit also includes a digitally-controlled delay line receiving an output of the down-sampling circuit, and an injection pulser receiving an output of the digitally-controlled delay line and connected to provide an injection pulse to a portion of the digital bang-bang phase-locked loop (PLL). The circuit further includes an injection timing calibration circuit connected to a control input of the digitally-controlled delay line. The circuit provides calibration of injection timing and bandwidth optimization, thereby reducing jitter in an output signal from the PLL.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 21, 2019
    Inventors: TING-KUEI KUAN, CHIN-YANG WU, RUEY-BIN SHEEN, CHIH-HSIEN CHANG
  • Patent number: 10164649
    Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Patent number: 10158364
    Abstract: A circuit having a tracking loop and a realignment loop is disclosed. The circuit includes: a phase frequency detector (PFD) module for comparing a phase difference of a first input signal and a second input signal; a pump module for converting PFD phase error to charge, wherein the pump module further comprises a low pass filter (LPF); an adjustable realignment module for adjusting a realignment strength, the adjustable realignment module receives a first plurality of inputs from the PFD module, the adjustable realignment module transmits a second plurality of outputs to the pump module; and a ring oscillator unit, the ring oscillator unit receives a first input from the pump module and a second input from the adjustable realignment module, and based on the first and second inputs produces a feedback signal.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsien Tsai, Cheng-Hsiang Hsieh, Chih-Hsien Chang, Ruey-Bin Sheen
  • Patent number: 10121781
    Abstract: A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: November 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao Chieh Li, Ruey-Bin Sheen, Chih-Hsien Chang
  • Publication number: 20180302096
    Abstract: Track-and-hold charge pumps and PLL are provided. A track-and-hold charge pump includes a track-and-hold circuit, a transconductance amplifier, a pulse width modulator (PWM), and a pumping switch coupled to the transconductance amplifier. The track-and-hold circuit samples an input signal according to a reference clock. The transconductance amplifier converts the sampled input signal into a current. The PWM provides a PWM signal according to the reference clock. The pumping switch is controlled by the PWM signal, to provide an output current according to the current.
    Type: Application
    Filed: April 18, 2017
    Publication date: October 18, 2018
    Inventors: Ting-Kuei KUAN, Cheng-Hsiang HSIEH, Chen-Ting KO, Ruey-Bin SHEEN, Chih-Hsien CHANG
  • Publication number: 20180287593
    Abstract: A ring oscillator is provided. The ring oscillator includes a pseudo pass-gate inverter, a third transistor, a fourth transistor and a delay chain. The pseudo pass-gate inverter includes a first transistor and a second transistor in series. The third transistor is connected in series with the pseudo pass-gate inverter. The drain of the fourth transistor is connected to an output of the pseudo pass-gate inverter. The gate of the fourth transistor is connected to the gate of the third transistor to receive the realignment signal. The delay chain includes a plurality of delay cells. An input of the delay chain is connected to the output of the pseudo pass-gate inverter. When the realignment signal is in a realignment state, the third transistor is turned off, the fourth transistor is turned on.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Tsung-Hsien TSAI, Ruey-Bin SHEEN, Chih-Hsien CHANG, Cheng-Hsiang HSIEH
  • Publication number: 20180152192
    Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.
    Type: Application
    Filed: February 9, 2017
    Publication date: May 31, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsien TSAI, Ruey-Bin SHEEN, Chih-Hsien CHANG, Cheng-Hsiang HSIEH
  • Patent number: 9748241
    Abstract: A semiconductor device for simultaneous operation at two temperature ranges includes a substrate, a first transistor, and a second transistor. The substrate has a first active region and a second active region. The first transistor includes a plurality of gate stacks disposed in the first active region. The second transistor includes a plurality of gate stacks disposed in the second active region. A ratio of the number of the gate stacks of the second transistor to an area size of the second active region is less than a ratio of the number of the gate stacks of the first transistor to an area size of the first active region.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ruey-Bin Sheen, Chao-Chieh Li, Ying-Yu Hsu
  • Patent number: 9748933
    Abstract: An example circuit includes: a slew rate driver configured to provide an output voltage; a first voltage provider configured to provide a first input voltage to the slew rate driver in response to the output voltage being within a first range; and a second voltage provider configured to provide a second input voltage to the slew rate driver in response to the output voltage being within a second range. The slew rate driver is further configured to change the output voltage based at least in part on the first input voltage or the second input voltage.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chen-Ting Ko, Chih-Hsien Chang, Ruey-Bin Sheen
  • Publication number: 20170187356
    Abstract: An example circuit includes: a slew rate driver configured to provide an output voltage; a first voltage provider configured to provide a first input voltage to the slew rate driver in response to the output voltage being within a first range; and a second voltage provider configured to provide a second input voltage to the slew rate driver in response to the output voltage being within a second range. The slew rate driver is further configured to change the output voltage based at least in part on the first input voltage or the second input voltage.
    Type: Application
    Filed: December 28, 2015
    Publication date: June 29, 2017
    Inventors: Chen-Ting Ko, Chih-Hsien Chang, Ruey-Bin Sheen
  • Publication number: 20170154876
    Abstract: A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV.
    Type: Application
    Filed: February 14, 2017
    Publication date: June 1, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao Chieh LI, Ruey-Bin SHEEN, Chih-Hsien CHANG
  • Patent number: 9595474
    Abstract: A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: March 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao Chieh Li, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 9503061
    Abstract: A system and method is disclosed for adaptively adjusting a duty cycle of a signal between a first and second chip in a 3D architecture/stack for adaptively calibrating a chip in a 3D architecture/stack. In one embodiment, the system includes a first chip and a second chip located within the 3D chip stack, wherein the first chip generates a calibration signal, the second chip receives the calibration signal and compares it to a reference signal to generate a comparison signal that further compared to a reference duty signal to generate a reference duty comparison signal, that is then provided to the first chip to generate a drive signal that adjusts a duty cycle of the calibration signal.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Yu Hsu, Ruey-Bin Sheen, Chih-Hsien Chang
  • Publication number: 20160305999
    Abstract: A flicker noise measurement circuit includes a first section. The first section includes a plurality of first stages connected in series. The first section includes a first feedback switching element configured to selectively feedback an output of the plurality of first stages to an input of the plurality of first stages. The first section includes a first section connection switching element. The flicker noise measurement circuit includes a second section connected to the first section. The second section includes a plurality of second stages connected in series, wherein the first section connection switching element is configured to selectively connect the plurality of second stages to the plurality of first stages. The second section includes a second feedback switching element configured to selectively feedback an output of the plurality of second stages to the input of the plurality of first stages.
    Type: Application
    Filed: April 16, 2015
    Publication date: October 20, 2016
    Inventors: Chao Chieh LI, Ruey-Bin SHEEN
  • Publication number: 20160254260
    Abstract: A semiconductor device for simultaneous operation at two temperature ranges includes a substrate, a first transistor, and a second transistor. The substrate has a first active region and a second active region. The first transistor includes a plurality of gate stacks disposed in the first active region. The second transistor includes a plurality of gate stacks disposed in the second active region. A ratio of the number of the gate stacks of the second transistor to an area size of the second active region is less than a ratio of the number of the gate stacks of the first transistor to an area size of the first active region.
    Type: Application
    Filed: February 26, 2015
    Publication date: September 1, 2016
    Inventors: RUEY-BIN SHEEN, CHAO-CHIEH LI, YING-YU HSU
  • Patent number: 9363115
    Abstract: Systems and methods are disclosed for aligning multiple data bits by adjusting the timing of input lines for those data bits. Embodiments include a hierarchical structure for comparing the timing of multiple sets of bits. Other embodiments include aligning data bits from multiple chips in a 3D die stacking architecture.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: June 7, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Yu Hsu, Ruey-Bin Sheen, Shih-Hung Lan, Chih-Hsien Chang
  • Publication number: 20160118960
    Abstract: A system and method is disclosed for adaptively adjusting a duty cycle of a signal between a first and second chip in a 3D architecture/stack for adaptively calibrating a chip in a 3D architecture/stack. In one embodiment, the system includes a first chip and a second chip located within the 3D chip stack, wherein the first chip generates a calibration signal, the second chip receives the calibration signal and compares it to a reference signal to generate a comparison signal that further compared to a reference duty signal to generate a reference duty comparison signal, that is then provided to the first chip to generate a drive signal that adjusts a duty cycle of the calibration signal.
    Type: Application
    Filed: January 4, 2016
    Publication date: April 28, 2016
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Yu HSU, Ruey-Bin SHEEN, Chih-Hsien CHANG
  • Patent number: 9287252
    Abstract: A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hui Chen, Ruey-Bin Sheen, Yung-Chow Peng, Po-Zeng Kang, Chung-Peng Hsieh
  • Patent number: 9231585
    Abstract: A system and method is disclosed for adaptively adjusting a driving strength of a signal between a first and second chip in a 3D architecture/stack. This may be used to adaptively calibrate a chip in a 3D architecture/stack. The system may include a transmission circuit on one chip and a receiver circuit on another chip. Alternatively, the system may include a transmission and receiver circuit on just one chip.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Yu Hsu, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 9197199
    Abstract: A level shifter for converting between voltages of a core voltage range to voltages within a larger I/O voltage range. The level shifter has interconnected transistors implemented as core devices operable within the core voltage range. The level shifter is connected to first and second power connections at the I/O voltage range. A voltage clamping element implemented as a core device has a threshold voltage greater than or equal to the difference between the I/O voltage range and the core voltage range and configured to prevent overstressing the transistors with voltages beyond the core voltage range. The input to the level shifter is within the core voltage range. The level shifter output signal has a high level at the high voltage of the I/O voltage range and a low level at approximately one threshold voltage above the low voltage level of the core voltage range.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tien-Chien Huang, Ruey-Bin Sheen