Patents by Inventor Ruey-Hsin Liu

Ruey-Hsin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10686032
    Abstract: High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 10686065
    Abstract: A method includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, forming a first trench and a second trench through in the first semiconductor layer and the second semiconductor layer, wherein a width of the second trench is different from a width of the first trench, forming a dielectric region in the first trench and forming a first gate region in the first trench and over the dielectric region, and a second gate region in the second trench.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Patent number: 10686047
    Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having a concave profile that defines an upper boundary lower than an upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ta-Yuan Kung, Ruey-Hsin Liu, Chen-Liang Chu, Chih-Wen Yao, Ming-Ta Lei
  • Patent number: 10680100
    Abstract: The present disclosure relates to a high voltage transistor device having a field structure that includes at least one conduction unit, and a method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed over a substrate between a source region and a drain region located within the substrate. A dielectric layer laterally extends from over the gate electrode to over a drift region between the gate electrode and the drain region. A field structure is located within the first ILD layer. The field structure includes a conduction unit having a vertically elongated shape and vertically extending from a top surface of the dielectric layer and a top surface of the first ILD layer.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chih Su, Hsueh-Liang Chou, Ruey-Hsin Liu
  • Patent number: 10680019
    Abstract: Some embodiments of the present disclosure relate to a method of forming a transistor. The method includes forming a gate dielectric over a substrate and forming a gate over the gate dielectric. The gate includes polysilicon extending between a first outermost sidewall and a second outermost sidewall of the gate. A mask is formed over the gate. The mask exposes a first gate region extending to the first outermost sidewall and covers a second gate region extending between the first gate region and the second outermost sidewall. Dopants are selectively implanted into the first gate region according to the mask. Source and drain regions are formed within the substrate. The source region and the drain region are asymmetric with respect to an interface of the first gate region and the second gate region and extend to substantially equal distances past the first and second outermost sidewalls of the gate, respectively.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Liang Chu, Chih-Wen Albert Yao, Ruey-Hsin Liu, Ming-Ta Lei
  • Patent number: 10672904
    Abstract: A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yogendra Yadav, Chi-Chih Chen, Ruey-Hsin Liu, Chih-Wen Yao
  • Patent number: 10658482
    Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ming-Ta Lei, Ruey-Hsin Liu, Shih-Fen Huang
  • Publication number: 20200105901
    Abstract: A method of making a triple well isolated diode includes forming a buried layer in a substrate. The method further includes forming an epi-layer over the substrate and the buried layer. The method further includes forming a first well in the epi-layer, wherein the first well forms an interface with the buried layer. The method further includes forming a second well in the epi-layer surrounding the first well. The method further includes forming a third well in the epi-layer surrounding the second well. The method further includes forming a deep well in the epi-layer beneath the first well to electrically connect to the second well. The method further includes forming a first plurality of isolation features between the first well and the second well. The method further includes forming a second plurality of isolation features between the third well and the epi-layer.
    Type: Application
    Filed: December 2, 2019
    Publication date: April 2, 2020
    Inventors: Chih-Chang CHENG, Fu-Yu CHU, Ruey-Hsin LIU
  • Publication number: 20200035826
    Abstract: An LDMOS transistor with a dummy gate comprises an extended drift region over a substrate, a drain region in the extended drift region, a channel region in the extended drift region, a source region in the channel region, a first dielectric layer with a first thickness formed over the extended drift region, a second dielectric layer with a second thickness formed over the extended drift region and the channel region, wherein the first thickness is greater than the second thickness, and wherein the first dielectric layer and the second dielectric layer form two steps, a first gate formed over the first dielectric layer and a second gate formed above the second dielectric layer.
    Type: Application
    Filed: October 1, 2019
    Publication date: January 30, 2020
    Inventors: Chun-Wai Ng, Ruey-Hsin Liu, Jun Cai, Hsueh-Liang Chou, Chi-Chih Chen
  • Publication number: 20200013888
    Abstract: The present disclosure relates to a high voltage transistor device having a field structure that includes at least one conduction unit, and a method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed over a substrate between a source region and a drain region located within the substrate. A dielectric layer laterally extends from over the gate electrode to over a drift region between the gate electrode and the drain region. A field structure is located within the first ILD layer. The field structure includes a conduction unit having a vertically elongated shape and vertically extending from a top surface of the dielectric layer and a top surface of the first ILD layer.
    Type: Application
    Filed: July 3, 2018
    Publication date: January 9, 2020
    Inventors: Po-Chih Su, Hsueh-Liang Chou, Ruey-Hsin Liu
  • Publication number: 20200006489
    Abstract: A transistor includes a first gate electrode and a second gate electrode over a substrate and on opposite sides of a drain region, a first source region and the drain region on opposite sides of the first gate electrode, a second source region and the drain region on opposite sides of the second gate electrode, a first doped well formed under the first source region, a second doped well formed under the first source region, wherein the first doped well is embedded in the second doped well, and wherein a doping density of the first doped well is greater than a doping density of the second doped well and a body contact region adjacent to the first source region, wherein sidewalls of the body contact region are aligned with sidewalls of the first source region from a top view.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Inventors: Hsueh-Liang Chou, Chun-Wai Ng, Po-Chih Su, Ruey-Hsin Liu
  • Patent number: 10510880
    Abstract: A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Ruey-Hsin Liu, Po-Chih Su
  • Patent number: 10497795
    Abstract: A triple well isolated diode including a substrate having a first conductivity type and a buried layer in the substrate. The buried layer has a second conductivity type opposite to the first conductivity type. The triple well isolated diode includes an epi-layer over the substrate and the buried layer. A portion of the epi-layer having the first conductivity type contacts the buried layer. The triple well isolated diode includes a first well, a second well, a third well and a deep well in the epi-layer. The first well and the third well have the second conductivity type. The second well and the deep well have the first conductivity type. The second well surrounds sides of the first well. The third well surrounds sides of the second well. The deep well extends beneath the first well to electrically connect to the second well on opposite sides of the first well.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ruey-Hsin Liu
  • Publication number: 20190363165
    Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having a concave profile that defines an upper boundary lower than an upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.
    Type: Application
    Filed: May 23, 2018
    Publication date: November 28, 2019
    Inventors: TA-YUAN KUNG, RUEY-HSIN LIU, CHEN-LIANG CHU, CHIH-WEN YAO, MING-TA LEI
  • Patent number: 10453955
    Abstract: An LDMOS transistor with a dummy gate comprises an extended drift region over a substrate, a drain region in the extended drift region, a channel region in the extended drift region, a source region in the channel region, a first dielectric layer with a first thickness formed over the extended drift region, a second dielectric layer with a second thickness formed over the extended drift region and the channel region, wherein the first thickness is greater than the second thickness, and wherein the first dielectric layer and the second dielectric layer form two steps, a first gate formed over the first dielectric layer and a second gate formed above the second dielectric layer.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Ruey-Hsin Liu, Jun Cai, Hsueh-Liang Chou, Chi-Chih Chen
  • Publication number: 20190267377
    Abstract: A device includes a vertical transistor comprising a first gate in a first trench, wherein the first gate comprises a dielectric layer and a gate region over the dielectric layer, and a second gate in a second trench, a high voltage lateral transistor immediately adjacent to the vertical transistor and a low voltage lateral transistor, wherein the high voltage lateral transistor is between the vertical transistor and the low voltage lateral transistor.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 29, 2019
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Publication number: 20190252545
    Abstract: A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate.
    Type: Application
    Filed: April 19, 2019
    Publication date: August 15, 2019
    Inventors: YOGENDRA YADAV, CHI-CHIH CHEN, RUEY-HSIN LIU, CHIH-WEN YAO
  • Patent number: 10381259
    Abstract: A method of fabricating a semiconductor structure includes forming an isolation feature in a substrate, removing a portion of the isolation feature and a portion of the substrate underneath the removed portion of the isolation feature to form a trench in the substrate, and forming a trapping feature around a bottom portion of the trench. A first sidewall and a second sidewall of the trench are in direct contact with the isolation feature, and a bottom surface of the trench is below a bottom surface of the isolation feature.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: August 13, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Alex Kalnitsky, Chih-Wen Yao, Jun Cai, Ruey-Hsin Liu, Hsiao-Chin Tuan
  • Publication number: 20190237485
    Abstract: Some embodiments of the present disclosure relate to a method of forming a transistor. The method includes forming a gate dielectric over a substrate and forming a gate over the gate dielectric. The gate includes polysilicon extending between a first outermost sidewall and a second outermost sidewall of the gate. A mask is formed over the gate. The mask exposes a first gate region extending to the first outermost sidewall and covers a second gate region extending between the first gate region and the second outermost sidewall. Dopants are selectively implanted into the first gate region according to the mask. Source and drain regions are formed within the substrate. The source region and the drain region are asymmetric with respect to an interface of the first gate region and the second gate region and extend to substantially equal distances past the first and second outermost sidewalls of the gate, respectively.
    Type: Application
    Filed: April 12, 2019
    Publication date: August 1, 2019
    Inventors: Chen-Liang Chu, Chih-Wen Albert Yao, Ruey-Hsin Liu, Ming-Ta Lei
  • Publication number: 20190189793
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.
    Type: Application
    Filed: February 12, 2019
    Publication date: June 20, 2019
    Inventors: CHIH-CHANG CHENG, FU-YU CHU, RUEY-HSIN LIU, KUANG-HSIN CHEN, CHIH-HSIN KO, SHIH-FEN HUANG