Abstract: An input/output data rate synchronization system includes a first data buffer that receives input data at a first rate, that temporarily stores the input data, and that outputs the input data at a second rate. A data processing module receives the input data from the first data buffer and outputs processed data at a third rate. A second data buffer receives the processed data from the data processing module at the third rate, temporarily stores the processed data, and outputs the processed data at a fourth rate. The data processing module temporarily stops receiving the input data and generating the processed data when the second data buffer exceeds a first predetermined capacity. The data processing module increases the second rate when the first data buffer exceeds a second predetermined capacity and decreases the second rate when a difference between the second and first rates is greater than a predetermined rate.

Abstract: A physical layer device includes a cable tester that determines a cable status of a cable and that includes a test module. The test module transmits a test pulse on the cable, measures a reflection amplitude, calculates a cable length, and determines the cable status based on the measured amplitude and the calculated cable length. An insertion loss estimator communicates with the cable tester, and estimates insertion loss of the cable based at least in part on a feedback equalizer gain.

Abstract: A high-speed decoder includes a buffer that includes buffer space for Q encoded data frames, where Q is a rational number greater than or equal to two. An iterative decoder receives the data frames from the buffer, generates a confidence result with each decoding iteration, and completes decoding a data frame when at least one of the number of iterations reaches a predetermined maximum number of iterations and the confidence result is greater than or equal to a predetermined confidence level. The iterative decoder stops decoding the Q data frames after a predetermined total number of iterations that is less than Q times the predetermined maximum number of iterations.

Abstract: A digital controller that controls an output regulator includes controller sub-blocks that perform sub-functions of the digital controller, wherein at least one of the controller sub-blocks includes at least one of a delay line and a first comparator. A controller monitors output power states of the output regulator and controls flow of power to the at least one of the controller sub-blocks of the digital controller to reduce power consumption of the digital controller during selected ones of the output power states of the output regulator.

Abstract: An output regulator includes a plurality of switch arrays. A controller enables selected ones of the plurality of switch arrays in response to a sense signal. The sense signal is based on an output of the output regulator. The controller generates drive signals to control the selected ones of the plurality of switch arrays. The controller adjusts first selected pulses in an output phase of the selected ones of the plurality of switch arrays based on a first pulse width. The controller adjusts second selected pulses in the output phase of the selected ones of the plurality of switch arrays based on a second pulse width greater than or less than the first pulse width.

Abstract: An RF receiver image rejection scheme. The RF is received and mixed in two quadrature channels allowing separation of the undesired image portion within the RF signal from the desired portion. The two channels can be summed to allow the image portions to cancel out and form a signal which is predominantly based on the desired portion. Another sum of the two channels can also be made to provide a signal which is primarily based on the image portion. Since there are some components of the image portion even in the compensated desired signal, that signal indicative of the image portion is used to compensate for that undesired portion.

Abstract: An output regulator comprises M switch arrays, where M is an integer greater than 2. A controller selectively enables N of the M switch arrays in response to a sense signal. The sense signal is based on an output of the output regulator. The controller generates drive signals to control the N of the M switch arrays, where N is an integer greater than or equal to 0 and less than or equal to M. When N is greater than 0, the controller dynamically sets a phase interval between the N of the M switch arrays to one of greater than 360/N or less than 360/N.

Abstract: A noise shaping module comprises a first addition module that receives an input signal. A modulo operation module generates a modulo signal based on an output of the addition module. A truncation module truncates the modulo output to form a truncated signal. A feedback filter module generates a feedback signal that is an input to the first addition module based on the truncated signal.

Abstract: Methods and apparatus describe techniques for reducing interference signals in a communication signal. A communication signal is received through a receiver. The communication signal contains an interference signal. A digital replica of the interference signal is generated, the digital replica is converted into a corresponding analog replica of the interference signal. The analog replica of the interference signal is subtracted from the communication signal.

Abstract: A device comprising an integrated circuit including at least one circuit block having an operating mode controlled in response to an enable signal or a clock signal. The circuit block receives a load current to power the circuit block, an amplitude of the load current being a function of the operating mode of the circuit block. The integrated circuit includes a weighting circuit to generate a weighting signal to indicate an expected amplitude of the load current of the integrated circuit. The weighting circuit monitors at least one of the enable signal and the clock signal and determines the expected amplitude of the load current as a function of the at least one of the enable signal and the clock signal.

Abstract: A power supply supplies an output current to an integrated circuit having at least one circuit block. The at least one circuit block has an operating mode controllable in response to an enable signal or a clock signal. The integrated circuit receives a load current to power the circuit block as a function of the operating mode of the circuit block. The load current is a portion of the output current. A receiver receives a weighted signal. The weighted signal is a function of the enable signal and the clock signal to indicate an expected load current of the integrated circuit. A controller controls the output current of the power supply as a function of the expected load current of the integrated circuit such that the power supply pre-emptively changes the output current.

Abstract: Circuitry for providing non-uniform analog-to-digital (“A/D”) signal conversion for wideband signals is provided. The circuitry of the invention is optimized for wideband signals because it does not sacrifice the small-scale resolution of high-probability signal amplitudes while preventing the clipping of low-probability signal amplitudes. The circuitry includes a nonlinear amplifier and an A/D converter that may be uniform or non-uniform. The digital output of the A/D converter may be further processed by circuitry that has an output function that is the inverse of that of the nonlinear amplifier, so as to maintain linear A/D conversion.

Abstract: A control system for controlling a power supply having an operating function. The power supply to supply an output current to an integrated circuit having at least one circuit block that is controllable by an enable signal or a clock signal. A receiver to receive the enable signal. A controller to determine a loading status of the at least one circuit block as a function of the enable signal or the clock signal and to control the output current of the power supply as a function of the loading status of the at least one circuit block such that the power supply pre-emptively changes the output current.

Abstract: A nonlinear echo compensator comprises a mapping circuit that includes a weighting circuit that generates a weighted signal based on a current symbol and a prior symbol and a function generating circuit that selects one of N functions based on the weighted signal, where N is an integer greater than one. The mapping circuit generates a driving signal based on the selected one of the N functions and the weighted signal. A canceling circuit generates a nonlinear echo compensation signal based on the driving signal.

Abstract: A noise shaping module comprises a first addition module that receives a digital input signal and generates an output signal. A truncation module generates a truncated output signal based on an output of said first addition module. A filter module generates a filtered output based on a combination of output signal of the first addition module and the truncated output signal of the first truncation module.

Abstract: A noise shaping circuit and method for operating the same includes a first addition module that receives a digital input signal. A first filter module generates a first filtered output signal based on an output of the first addition module. A truncation module generates a truncated output signal based on first filtered output signal. A second filter module generates a second filtered output signal based on the truncated output signal. The second filtered output signal is an input to the first addition module.

Abstract: A signal processing apparatus includes an input circuit to receive an input signal, and a high-pass filter responsive to the input circuit. The high-pass filter includes M taps to filter precursor intersymbol interference (ISI), one main tap and N taps to filter postcursor ISI. Each of n taps of the N taps is limited to a range of between ?1 and 0. The signal processing apparatus includes a decision feedback equalizer. The decision feedback equalizer includes a decision circuit responsive to the high-pass filter, and a feedback filter responsive to the decision circuit. The decision circuit is responsive to the feedback filter.

Abstract: A control system for controlling a power supply having an operating function. The power supply to supply an output current to an integrated circuit having at least one circuit block that is controllable by an enable signal or a clock signal. A receiver to receive the enable signal. A controller to determine a loading status of the at least one circuit block as a function of the enable signal or the clock signal and to control the output current of the power supply as a function of the loading status of the at least one circuit block such that the power supply preemptively changes the output current.

Abstract: A duty cycle estimator determines a duty cycle for controlling a regulated output of an output regulator. The output regulator is responsive to the duty cycle for controlling a transfer of energy between an input source and the regulated output. An error generator compares the regulated output to an output reference to generate an output error. An accumulator determines an accumulated error of the output error over a time period of at least N times a switching period of the output regulator, where N is an integer. A reference generator generates reference levels. A comparator compares the accumulated error to the reference levels such that a single zero is generated, and generates the duty cycle based on the comparing.

Abstract: A method of sensing current comprises providing a current sensor having a gain resolution; setting the gain resolution of the current sensor to an initial resolution; sensing current flowing through the current sensor; evaluating an amplitude of the current; and changing the gain resolution of the current sensor based on the evaluating.

Abstract: A wood particle screen particularly useful for separating fines from wood chips in which a bed of flexible foraminous material having holes therein sized to permit fines to pass therethrough is flexibly mounted for receiving a flow of wood chips and fines thereon. Beater rolls are disposed beneath the screening bed, each including a plurality of spaced beater bars so positioned as to contact the bottom of the screening bed as the bars rotate through the uppermost position of the rolls.