Abstract: A circuit determines a sampling phase of a sampling clock of an analog-to-digital converter in a receiver of a communication system. The apparatus adjusts the sampling clock of an analog-to-digital converter in a receiver of a communication system based on the determined sampling phase of the sampling clock to remove a first intersymbol interference from a signal received by the receiver. An open loop filter removes any remaining intersymbol interference from the received signal. This is to insure that the receiver within a communication system that the adaptive equalization necessary to eliminate precursor and postcursor intersymbol interference is decoupled and independent.

Abstract: Circuitry for providing non-uniform analog-to-digital (“A/D”) signal conversion for wideband signals is provided. The circuitry of the invention is optimized for wideband signals because it does not sacrifice the small-scale resolution of high-probability signal amplitudes while preventing the clipping of low-probability signal amplitudes. The circuitry includes a nonlinear amplifier and an A/D converter that may be uniform or non-uniform. The digital output of the A/D converter may be further processed by circuitry that has an output function that is the inverse of that of the nonlinear amplifier, so as to maintain linear A/D conversion.

Abstract: A power supply supplies an output current to an integrated circuit having at least one circuit block. The at least one circuit block has an operating mode controllable in response to an enable signal or a clock signal. The integrated circuit receives a load current to power the circuit block as a function of the operating mode of the circuit block. The load current is a portion of the output current. A receiver receives a weighted signal. The weighted signal is a function of the enable signal and the clock signal to indicate an expected load current of the integrated circuit. A controller controls the output current of the power supply as a function of the expected load current of the integrated circuit such that the power supply preemptively changes the output current.

Abstract: A device comprising an integrated circuit including at least one circuit block having an operating mode controlled in response to an enable signal or a clock signal. The circuit block receives a load current to power the circuit block, an amplitude of the load current being a function of the operating mode of the circuit block. The integrated circuit includes a weighting circuit to generate a weighting signal to indicate an expected amplitude of the load current of the integrated circuit. The weighting circuit monitors at least one of the enable signal and the clock signal and determines the expected amplitude of the load current as a function of the at least one of the enable signal and the clock signal.

Abstract: A physical layer device including a first port and a second port comprises a cable tester that communicates with the first and second ports and that determines a cable status, which includes an open status, a short status, and a normal status. Opposite ends of a cable selectively communicate with the first and second ports. The cable tester includes a test module that transmits a test pulse on the cable, measures reflection amplitude, calculates a cable length, and determines the cable status based on the measured amplitude and the calculated cable length. A frequency synthesizer communicates with the cable and that selectively outputs a plurality of signals at a plurality of frequencies on the first port. An insertion loss calculator receives the signals on the second port and that estimates insertion loss.

Abstract: A cable tester tests cable to determine a cable status. The cable status includes an open status, a normal status and a short status. A pretest module senses activity on the cable and selectively enables testing based on said sensed activity. A test module is enabled by the pretest module, transmits a test pulse on the cable, measures a reflection amplitude and calculates a cable length. The test module determines the cable status based on the measured amplitude and the calculated cable length.

Abstract: A cable tester includes a pretest module that senses activity on a cable and selectively enables testing depending upon the sensed activity. A test module is enabled by the pretest module, transmits test pulses on the cable, measures a refelction amplitude, calculates a cable length, and determines a cable status based on the measures amplitude and the calculated cable length. A polarity detector communicates with the cable tester and detects a polarity of at least one pair of the cable. The test module senses activity on a first pair of the cable, enables testing if activity is not detected for a first period, and enables testing of the first pair if, during the first period, activity is detected on the first pair and is subsequently not detected on the first pair for a second period after the activity is detected.

Abstract: A duty cycle limiter for limiting a transfer of energy between an input source and a regulated output of an output regulator. The output regulator having a regulator characteristic and a computed duty cycle for controlling the transfer of energy between the input source and the regulated output. The duty cycle limiter including a digital controller to generate a reference level and to compare the regulator characteristic of the output regulator to the reference level to determine a maximum duty cycle. The digital controller to control the reference level at a frequency at least equal to a switching frequency of the output regulator. The digital controller to limit the computed duty cycle to the maximum duty cycle.

Abstract: A digital controller for controlling an output regulator. The digital controller having sub-blocks for providing functions to control the output regulator. An energy saving discontinuous mode (ESDM) controller to monitor a sense point of the output regulator. The sense point to indicate a power state of the output regulator and the ESDM controller to control a flow of power to the sub-blocks to control power consumption of the digital controller as a function of the power state of the output regulator.

Abstract: A physical layer device includes a cable tester that determines a cable status. A test module transmits a test pulse on the cable, measures reflection amplitude, calculates a cable length, and determines the cable status based on the measured amplitude and the calculated cable length. A first digital signal processor (DSP) communicates with a first pair of the cable and includes a first echo canceller having a finite impulse response (FIR) filter with taps and a first crosstalk canceller having a FIR filter with taps. A second DSP communicates with a second pair of the cable and includes a second echo canceller having a FIR filter with taps and a second crosstalk canceller having a FIR filter with taps. The cable tester calculates a distance to at least one of echo and crosstalk based on values of the taps of the first echo canceller and the second crosstalk canceller.

Abstract: An output regulator to convert an input voltage to a regulated output. The output regulator including a power stage to generate a power output from the input voltage. An output filter to filter the power output to generate the regulated output. An output sensor to generate a digital sense signal to indicate within which of at least three reference ranges the regulated output is included. Each of the at least three reference ranges including a plurality of possible values of the regulated output. A digital controller, responsive to the digital sense signal, to generate a drive signal to control the power stage.

Abstract: A physical layer device communicates over a cable and includes a cable tester that determines a cable status. The cable tester includes a pretest module that senses activity on the cable. A test module transmits a test pulse on the cable, measures reflection amplitude, calculates a cable length, and determines the cable status based on the measured amplitude and the calculated cable length. A first digital signal processor (DSP) communicates with a first pair of the cable and includes a first echo canceller and a first finite impulse response filter with first taps. A second DSP communicates with a second pair of the cable and includes a second echo canceller and a second finite impulse response filter with second taps. At least one of the physical layer device and the cable tester estimates skew between the first and second pairs based on values of the first and second taps.

Abstract: A control system to control an output regulator. The output regulator to convert an input voltage to a regulated output. The output regulator including a power stage to generate a power output from the input voltage and an output filter to filter the power output to generate the regulated output. A digital controller, responsive to a sense signal corresponding to the regulated output, to generate a drive signal to control the power stage.

Abstract: A physical layer device is provided that includes an autonegotiation circuit that negotiates a link with a link partner at first and second link speeds. The physical layer device also includes a cable tester that tests a cable and that determines a cable status of the cable before autonegotiation circuit negotiates the link at the first and second link speeds.

Abstract: A physical layer device communicates with a second physical layer device over a cable. The physical layer device includes a cable tester that identifies when the second physical layer device is disconnected from the cable. The cable tester includes a test initiating circuit that initiates a cable test when a link is lost, a test module that transmits test pulses on the pairs of the cable, measures reflection amplitudes, calculates cable lengths, and determines whether the pairs have said open status based on said measured amplitude and said calculated cable length, and a reporting circuit that generates a disconnect signal when at least one of the pairs has an open status.

Abstract: A detection circuit or a perpendicular recording system includes a channel circuit to amplify the read data signal. A transient detector generates a transient detect signal. A first path and a second path are coupled to an output of the channel circuit. The first path includes a first data detector that generates a first detected data signal in response to detecting data in the read data signal. A second path includes a series connected combination of a data filter and a second data detector. The filter generates a filtered data signal in which low frequency components of the read data signal are attenuated. The second data detector generates a second detected data signal in response to detecting data in the filtered data signal. Either the first detected data signal or the second detected data signal is coupled to a data processor based on whether a transient is detected.

Abstract: Methods, software, circuits, architectures, and systems for encoding, decoding and error checking/correcting information, particularly pulse amplitude modulated information. The present invention enjoys particular advantage when used to encode x-unit sequence values of N-ary information into y-unit sequence values of M-ary information and to decode y-unit sequence values of M-ary information into x-unit sequence values of N-ary information, where Nx<My (and particularly where Nx<My, but Nx>My?M). The present invention advantageously provides a straight-forward mechanism for coding information that enables one to take advantage of coding overhead (e.g., unused states in the encoded, transmitted sequence) to accomplish other coding objectives, such as conforming to coding constraints, reducing transmission errors (or increasing the likelihood of successfully correcting such errors), dc balancing the coded information, and under certain conditions, even reducing power consumption.

Abstract: A physical layer device including a first port, a second port, and a cable that has one end that communicates with the first port and an opposite end that communicates with the second port. A cable tester tests the cable to determine a cable status, which includes an open status, a short status, and a normal status. A pretest module senses activity on the cable and selectively enables testing depending upon the sensed activity. A test module transmits a test pulse on the cable, measures a reflection amplitude, calculates a cable length, and determines the cable status based on the measured amplitude and the calculated cable length. A frequency synthesizer communicates with the cable and that selectively outputs a plurality of signals at a plurality of frequencies on the first port. An insertion loss calculator receives the signals on the second port and that estimates insertion loss.

Abstract: A digital controller for controlling a regulated output of an output regulator. The output regulator responsive to a pulse width signal for controlling the transfer of energy between an input source and the regulated output. The digital controller including a duty cycle estimator to determine a nominal duty cycle. An adjust determiner to determine an adjustment value to combine with the nominal duty cycle to generate an adjusted duty cycle. The pulse width signal being a function of the adjusted duty cycle.

Abstract: A cable tester tests cable and determines a cable pass/fail status. A pretest module senses activity on the cable and selectively enables testing based on the sensed activity. A test module is enabled by the pretest module, transmits a test pulse on the cable, measures a reflection amplitude, and calculates a cable length. The cable status includes an open status, a short status, and a normal status. The test module determines the cable status of the cable based on the cable at least one of passing and failing A out of B cable tests. The test module determines the cable status for each of the B tests based on the measured amplitude and the calculated cable length.