Patents by Inventor Runsheng He

Runsheng He has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060013023
    Abstract: A closed-loop control system for a DC/DC converter includes a DC/DC converter that receives a first DC voltage and that generates a second DC voltage. The DC/DC converter includes first and second inductances. A control module receives the second DC voltage and generates at least one control signal to one of charge or discharge the first and second inductances. The control module has first and second modes. During the first mode the control module alternately charges one of the first and second inductances and discharges the other of the first and second inductances. During the second mode the control module one of charges or discharges both of the first and second inductances. The control module initiates the second mode when a transient condition occurs in the DC/DC converter. The transient condition is based on one of the second DC voltage and current through an output capacitance in the DC/DC converter.
    Type: Application
    Filed: July 13, 2004
    Publication date: January 19, 2006
    Applicant: Marvell World Trade Ltd.
    Inventors: Runsheng He, Zhipei Chi
  • Patent number: 6982557
    Abstract: A physical layer device according to some implementations includes a cable tester that generates a test pulse on a cable and that determines a cable status including an open status, a short status, and a normal status. A cable impedance estimator communicates with the cable tester and estimates an impedance of the cable based on a reflection amplitude of the test pulse.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: January 3, 2006
    Assignee: Marvell International, Ltd.
    Inventors: William Lo, Yiqing Guo, Tak Tsui, Tsin-Ho Leung, Runsheng He, Eric Janofsky
  • Patent number: 6979988
    Abstract: A duty cycle estimator for determining a nominal duty cycle of an output regulator. The duty cycle estimator having at least two modes and including at least a mode one estimator and a mode two estimator. The mode one estimator to determine the nominal duty cycle as a function of prior duty cycles. The mode two estimator to determine the nominal duty cycle as a function of accumulated error. A mode selector, based on a mode selection criteria, to select a one of the at least two modes to generate the nominal duty cycle.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: December 27, 2005
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Patent number: 6980007
    Abstract: A physical layer device that communicates over a cable comprises a cable tester that determines a cable status, which includes an open status, a short status, and a normal status. The cable tester includes a pretest module that senses activity on the cable and selectively enables testing based on the sensed activity. A test module is enabled by the pretest module, transmits a test pulse on the cable, measures a reflection amplitude, calculates a cable length, and determines the cable status based on the measured amplitude and the calculated cable length. An insertion loss estimator communicates with the cable tester and estimates insertion loss of the cable. A return loss estimator communicates with the cable tester and estimates return loss of the cable based on gain parameters of the physical layer device.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: December 27, 2005
    Assignee: Marvell International Ltd.
    Inventors: William Lo, Yiqing Guo, Tak Tsui, Tsin-Ho Leung, Runsheng He, Eric Janofsky
  • Patent number: 6977492
    Abstract: A control system for controlling an output regulator having a regulated output. The control system including an output sensor to generate a digital sense signal to indicate within which of at least three reference ranges the regulated output is included. Each of the at least three reference ranges including a plurality of possible values of the regulated output. A digital controller, responsive to the digital sense signal, to generate a drive signal to control the regulated output.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: December 20, 2005
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Patent number: 6956510
    Abstract: Methods, software, circuits, architectures, and systems for encoding, decoding and error checking/correcting information, particularly pulse amplitude modulated information. The present invention enjoys particular advantage when used to encode x-unit sequence values of N-ary information into y-unit sequence values of M-ary information and to decode y-unit sequence values of M-ary information into x-unit sequence values of N-ary information, where Nx<My (and particularly where Nx<My, but Nx>My?M). The present invention advantageously provides a straight-forward mechanism for coding information that enables one to take advantage of coding overhead (e.g., unused states in the encoded, transmitted sequence) to accomplish other coding objectives, such as conforming to coding constraints, reducing transmission errors (or increasing the likelihood of successfully correcting such errors), dc balancing the coded information, and under certain conditions, even reducing power consumption.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: October 18, 2005
    Assignee: Marvell International Ltd.
    Inventors: Runsheng He, Kok-Wui Cheong
  • Patent number: 6933711
    Abstract: A circuit for generating a feedback signal corresponding to a regulated output. The circuit including a reference generator to generate at least two reference levels, the reference levels to define at least three reference ranges. A comparator to compare the regulated output to the at least three reference ranges. The comparator to generate a digital signal to indicate within which of the at least three reference ranges the regulated output is included.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: August 23, 2005
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Publication number: 20050156581
    Abstract: A power array for converting an input voltage to a chopped output used in an output regulator that converts the chopped output to a regulated output. The power array including a switch array, responsive to independent drive signals, to convert the input voltage to the chopped output at a switching frequency. The switch array including at least two power switches. A switch controller to generate the independent drive signals as a function of a duty cycle signal. The switch controller to operate at a sampling frequency, the sampling frequency being greater than the switching frequency. The switch controller to control the independent drive signals at a drive frequency greater than the switching frequency.
    Type: Application
    Filed: March 15, 2005
    Publication date: July 21, 2005
    Applicant: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Patent number: 6894465
    Abstract: A power array for converting an input voltage to a chopped output used in an output regulator that converts the chopped output to a regulated output. The power array including a switch array, responsive to independent drive signals, to convert the input voltage to the chopped output at a switching frequency. The switch array including at least two power switches. A switch controller to generate the independent drive signals as a function of a duty cycle signal. The switch controller to operate at a sampling frequency, the sampling frequency being greater than the switching frequency. The switch controller to control the independent drive signals at a drive frequency greater than the switching frequency.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: May 17, 2005
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Patent number: 6870881
    Abstract: A feedforward equalizer for DFE based detector is provided comprising a digital to analog converter to convert an analog signal to a digital signal. A feedforward equalizer comprises a high-pass filter and is responsive to the input circuit. The high-pass filter has a low cutoff frequency, has a relatively flat response and has high attenuation at low frequencies. A decision feedback equalizer comprises a decision circuit responsive to the feedforward equalizer, and a feedback filter is responsive to the decision circuit. The decision circuit is also responsive to the feedback filter.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: March 22, 2005
    Assignee: Marvell International Ltd.
    Inventor: Runsheng He
  • Publication number: 20050052163
    Abstract: A control system for controlling a multiphase output regulator having a regulated DC output and operating at a switching frequency. The multiphase output regulator including at least two switch arrays to generate individually controllable output phases that combine to form the regulated DC output. The control system comprising a digital controller operable at a sampling frequency greater than the switching frequency. The digital controller responsive to a sense signal corresponding to the regulated output, to generate array duty cycle signals to control each of the switch arrays. The digital controller to control the array duty cycle signals at the sampling frequency and to dynamically set a phase interval between each of the output phases.
    Type: Application
    Filed: September 4, 2003
    Publication date: March 10, 2005
    Applicant: Marvell International Ltd.
    Inventors: Sehat Sutardja, Runsheng He
  • Patent number: 6856790
    Abstract: A circuit employing dual adaptive D.C. noise cancellation loops to eliminate D.C. noise from a signal received from a communication channel. The circuit employing the two adaptive D.C. noise cancellation loops is constructed such that the two adaptive D.C. noise cancellation loops are decoupled to insured stability of the circuit while eliminating the D.C. noise components from a signal received from a communication channel. A first D.C. noise canceler generates a first D.C. noise cancellation signal that is a product of an error signal that is an estimate of noise within the signal and a first D.C. gain constant. The first D.C. Noise is connected within the receiver to an input of a decision circuit that subtractively combines the first D.C. noise cancellation signal with the signal to remove a first portion of the D.C. noise components. A second D.C. noise canceler additively restores the first D.C. noise cancellation signal to the error signal and multiplies the restored error signal with the first D.C.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: February 15, 2005
    Assignee: Marvell International Ltd.
    Inventor: Runsheng He
  • Publication number: 20040239300
    Abstract: A digital controller for controlling an output regulator. The digital controller having sub-blocks for providing functions to control the output regulator. An energy saving discontinuous mode (ESDM) controller to monitor a sense point of the output regulator. The sense point to indicate a power state of the output regulator and the ESDM controller to control a flow of power to the sub-blocks to control power consumption of the digital controller as a function of the power state of the output regulator.
    Type: Application
    Filed: April 19, 2004
    Publication date: December 2, 2004
    Applicant: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Publication number: 20040221182
    Abstract: A control system for controlling a power supply having an operating function. The power supply to supply an output current to an integrated circuit having at least one circuit block that is controllable by an enable signal or a clock signal. A receiver to receive the enable signal. A controller to determine a loading status of the at least one circuit block as a function of the enable signal or the clock signal and to control the output current of the power supply as a function of the loading status of the at least one circuit block such that the power supply pre-emptively changes the output current.
    Type: Application
    Filed: April 30, 2003
    Publication date: November 4, 2004
    Inventors: Runsheng He, Sehat Sutardja
  • Publication number: 20040196018
    Abstract: A duty cycle limiter for limiting a transfer of energy between an input source and a regulated output of an output regulator. The output regulator having a regulator characteristic and a computed duty cycle for controlling the transfer of energy between the input source and the regulated output. The duty cycle limiter including a digital controller to generate a reference level and to compare the regulator characteristic of the output regulator to the reference level to determine a maximum duty cycle. The digital controller to control the reference level at a frequency at least equal to a switching frequency of the output regulator. The digital controller to limit the computed duty cycle to the maximum duty cycle.
    Type: Application
    Filed: April 19, 2004
    Publication date: October 7, 2004
    Applicant: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Publication number: 20040196015
    Abstract: A duty cycle estimator for determining a nominal duty cycle of an output regulator. The duty cycle estimator having at least two modes and including at least a mode one estimator and a mode two estimator. The mode one estimator to determine the nominal duty cycle as a function of prior duty cycles. The mode two estimator to determine the nominal duty cycle as a function of accumulated error. A mode selector, based on a mode selection criteria, to select a one of the at least two modes to generate the nominal duty cycle.
    Type: Application
    Filed: April 19, 2004
    Publication date: October 7, 2004
    Applicant: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Publication number: 20040196017
    Abstract: A circuit for generating a feedback signal corresponding to a regulated output. The circuit including a reference generator to generate at least two reference levels, the reference levels to define at least three reference ranges. A comparator to compare the regulated output to the at least three reference ranges. The comparator to generate a digital signal to indicate within which of the at least three reference ranges the regulated output is included.
    Type: Application
    Filed: April 19, 2004
    Publication date: October 7, 2004
    Applicant: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Publication number: 20040196016
    Abstract: A digital controller for controlling a regulated output of an output regulator. The output regulator responsive to a pulse width signal for controlling the transfer of energy between an input source and the regulated output. The digital controller including a duty cycle estimator to determine a nominal duty cycle. An adjust determiner to determine an adjustment value to combine with the nominal duty cycle to generate an adjusted duty cycle. The pulse width signal being a function of the adjusted duty cycle.
    Type: Application
    Filed: April 19, 2004
    Publication date: October 7, 2004
    Applicant: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Publication number: 20040183510
    Abstract: A power array for converting an input voltage to a chopped output used in an output regulator that converts the chopped output to a regulated output. The power array including a switch array, responsive to independent drive signals, to convert the input voltage to the chopped output at a switching frequency. The switch array including at least two power switches. A switch controller to generate the independent drive signals as a function of a duty cycle signal. The switch controller to operate at a sampling frequency, the sampling frequency being greater than the switching frequency. The switch controller to control the independent drive signals at a drive frequency greater than the switching frequency.
    Type: Application
    Filed: April 5, 2004
    Publication date: September 23, 2004
    Applicant: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Publication number: 20040178785
    Abstract: A control system to control an output regulator. The output regulator to convert an input voltage to a regulated output. The output regulator including a power stage to generate a power output from the input voltage and an output filter to filter the power output to generate the regulated output. A digital controller, responsive to a sense signal corresponding to the regulated output, to generate a drive signal to control the power stage.
    Type: Application
    Filed: March 26, 2004
    Publication date: September 16, 2004
    Applicant: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang