Patents by Inventor Ryan Hsin-Chin Jiang
Ryan Hsin-Chin Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9025289Abstract: A low-cost ESD protection device for high-voltage open-drain pad is disclosed, which has a first high-voltage (HV) NMOSFET coupled to a high-voltage (HV) open drain pad, a ground pad, a HV block unit and an ESD clamp unit and a low-voltage (LV) bias unit coupled to the first HV NMOSFET, a low-voltage (LV) trigger, the ESD clamp unit and the ground pad. The LV trigger is coupled to the HV block unit. The HV block unit blocks a high voltage from the HV open drain pad diode during normal operation and generates a trigger signal to the LV trigger when an ESD event is applied to the HV open drain pad. Then, the LV trigger turns on the ESD clamp unit to discharge an ESD current and switches the LV bias unit to turn off the first HV NMOSFET.Type: GrantFiled: December 12, 2013Date of Patent: May 5, 2015Assignee: Amazing Microelectronic Corp.Inventors: James Jeng-Jie Peng, Chih-Hao Chen, Ryan Hsin-Chin Jiang
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Patent number: 9024516Abstract: A method for fabricating a semiconductor-based planar micro-tube discharger structure is provided, including the steps of forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap, forming an insulating layer over the patterned electrodes and the separating block, and filling the insulating layer into the gap. At least two discharge paths are formed. The method can fabricate a plurality of discharge paths in a semiconductor structure, the structure having very high reliability and reusability.Type: GrantFiled: December 17, 2013Date of Patent: May 5, 2015Assignee: Amazing Microelectronic Corp.Inventors: Tung-Yang Chen, Ming-Dou Ker, Ryan Hsin-Chin Jiang
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Publication number: 20150041848Abstract: A silicon-controlled rectification device with high efficiency is disclosed, which comprises a P-type region surrounding an N-type region. A first P-type heavily doped area is arranged in the N-type region and connected with a high-voltage terminal. A plurality of second N-type heavily doped areas is arranged in the N-type region. A plurality of second P-type heavily doped areas is closer to the second N-type heavily doped areas than the first N-type heavily doped area and arranged in the P-type region. At least one third N-type heavily doped area is arranged in the P-type region and connected with a low-voltage terminal. Alternatively or in combination, the second N-type heavily doped areas and the second P-type heavily doped areas are respectively arranged in the P-type region and the N-type region.Type: ApplicationFiled: August 6, 2013Publication date: February 12, 2015Applicant: AMAZING MICROELECTRONIC CORP.Inventors: TUNG-YANG CHEN, JAMES JENG-JIE PENG, WOEI-LIN WU, RYAN HSIN-CHIN JIANG
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Publication number: 20140299912Abstract: In a silicon-controlled-rectifier (SCR) with adjustable holding voltage, an epitaxial layer is formed on a heavily doped semiconductor layer. A first N-well having a first P-heavily doped area is formed in the epitaxial layer. A first P-well is formed in the epitaxial layer. Besides, a first N-heavily doped area is formed in the first P-well. At least one deep isolation trench is formed in the epitaxial layer, having a depth greater than the depth of the first N-type well and located between the first P-heavily doped area and the first N-heavily doped area. A distance between the deep isolation trench and the heavily doped semiconductor layer is larger than zero.Type: ApplicationFiled: June 19, 2014Publication date: October 9, 2014Inventors: Kun-Hsien LIN, Che-Hao CHUANG, Ryan Hsin-Chin JIANG
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Patent number: 8829775Abstract: The present invention discloses a semiconductor-based planar micro-tube discharger structure and a method for fabricating the same. The method comprises steps: forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap; forming an insulating layer over the patterned electrodes and the separating block and filling the insulating layer into the gap. Thereby are formed at least two discharge paths. The method can fabricate a plurality discharge paths in a semiconductor structure. Therefore, the structure of the present invention has very high reliability and reusability.Type: GrantFiled: May 4, 2012Date of Patent: September 9, 2014Assignee: Amazing Microelectric Corp.Inventors: Tung-Yang Chen, Ming-Dou Ker, Ryan Hsin-Chin Jiang
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Patent number: 8817437Abstract: A high voltage open-drain electrostatic discharge (ESD) protection device is disclosed, which comprises a high-voltage n-channel metal oxide semiconductor field effect transistor (HV NMOSFET) coupled to a high-voltage pad and a low-voltage terminal and receiving a high voltage on the high-voltage pad to operate in normal operation. The high-voltage pad and the HV NMOSFET are further coupled to a high-voltage ESD unit blocking the high voltage, and receiving a positive ESD voltage on the high-voltage pad to bypass an ESD current when an ESD event is applied to the high-voltage pad. The high-voltage ESD unit and the low-voltage terminal are coupled to a power clamp unit, which receives the positive ESD voltage via the high-voltage ESD unit to bypass the ESD current.Type: GrantFiled: January 3, 2013Date of Patent: August 26, 2014Assignee: Amazing Microelectronics Corp.Inventors: James Jeng-Jie Peng, Chih-Hao Chen, Ryan Hsin-Chin Jiang
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Patent number: 8785971Abstract: A transient voltage suppressor without leakage current is disclosed, which comprises a P-substrate. There is an N-type epitaxial layer formed on the P-substrate, and a first N-heavily doped area, a first P-heavily doped area, an electrostatic discharge (ESD) device and at least one deep isolation trench are formed in the N-epitaxial layer. A first N-buried area is formed in the bottom of the N-epitaxial layer to neighbor the P-substrate and located below the first N-heavily doped area and the first P-heavily doped area. The ESD device is coupled to the first N-heavily doped area. The deep isolation trench is not only adjacent to the first N-heavily doped area, but has a depth greater than a depth of the first N-buried area, thereby separating the first N-buried area and the ESD device.Type: GrantFiled: November 23, 2011Date of Patent: July 22, 2014Assignee: Amazing Microelectronic Corp.Inventors: Che-Hao Chuang, Kun-Hsien Lin, Ryan Hsin-Chin Jiang
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Patent number: 8773826Abstract: A power-rail ESD clamp circuit with a silicon controlled rectifier and a control module is provided. The silicon controlled rectifier is connected to a high voltage level and a low voltage level for bearing a current flow. The control module is connected to the silicon controlled rectifier in parallel, and includes a PMOS, a NMOS, at least one output diode, a resistor and a conducting string. The silicon controlled rectifier is a P+ or N+ triggered silicon controlled rectifier. By employing the novel power-rail ESD clamp circuit, it is extraordinarily advantageous of reducing both a standby leakage current and layout area while implementation.Type: GrantFiled: August 29, 2012Date of Patent: July 8, 2014Assignee: Amazing Microelectronic Corp.Inventors: Federico Agustin Altolaguirre, Ming-Dou Ker, Ryan Hsin-Chin Jiang
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Publication number: 20140185167Abstract: A high voltage open-drain electrostatic discharge (ESD) protection device is disclosed, which comprises a high-voltage n-channel metal oxide semiconductor field effect transistor (HV NMOSFET) coupled to a high-voltage pad and a low-voltage terminal and receiving a high voltage on the high-voltage pad to operate in normal operation. The high-voltage pad and the HV NMOSFET are further coupled to a high-voltage ESD unit blocking the high voltage, and receiving a positive ESD voltage on the high-voltage pad to bypass an ESD current when an ESD event is applied to the high-voltage pad. The high-voltage ESD unit and the low-voltage terminal are coupled to a power clamp unit, which receives the positive ESD voltage via the high-voltage ESD unit to bypass the ESD current.Type: ApplicationFiled: January 3, 2013Publication date: July 3, 2014Applicant: AMAZING MIRCOELECTRONIC CORP.Inventors: James Jeng-Jie PENG, Chih-Hao CHEN, Ryan Hsin-Chin JIANG
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Publication number: 20140106064Abstract: A method for fabricating a semiconductor-based planar micro-tube discharger structure is provided, including the steps of forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap, forming an insulating layer over the patterned electrodes and the separating block., and filling the insulating layer into the gap. At least two discharge paths are formed. The method can fabricate a plurality of discharge paths in a semiconductor structure, the structure having very high reliability and reusability.Type: ApplicationFiled: December 17, 2013Publication date: April 17, 2014Applicant: Amazing Microelectronic Corp.Inventors: Tung-Yang CHEN, Ming-Dou KER, Ryan Hsin-Chin JIANG
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Publication number: 20140063663Abstract: A power-rail ESD clamp circuit with a silicon controlled rectifier and a control module is provided. The silicon controlled rectifier is connected to a high voltage level and a low voltage level for bearing a current flow. The control module is connected to the silicon controlled rectifier in parallel, and includes a PMOS, a NMOS, at least one output diode, a resistor and a conducting string. The silicon controlled rectifier is a P+ or N+ triggered silicon controlled rectifier. By employing the novel power-rail ESD clamp circuit, it is extraordinarily advantageous of reducing both a standby leakage current and layout area while implementation.Type: ApplicationFiled: August 29, 2012Publication date: March 6, 2014Inventors: Federico Agustin ALTOLAGUIRRE, Ming-Dou Ker, Ryan Hsin-Chin Jiang
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Patent number: 8552530Abstract: A vertical transient voltage suppressor for protecting an electronic device is disclosed. The vertical transient voltage includes a conductivity type substrate having highly doping concentration; a first type lightly doped region is arranged on the conductivity type substrate, wherein the conductivity type substrate and the first type lightly doped region respectively belong to opposite types; a first type heavily doped region and a second type heavily doped region are arranged in the first type lightly doped region, wherein the first and second type heavily doped regions and the conductivity type substrate belong to same types; and a deep first type heavily doped region is arranged on the conductivity type substrate and neighbors the first type lightly doped region, wherein the deep first type heavily doped region and the first type lightly doped region respectively belong to opposite types, and wherein the deep first type heavily doped region is coupled to the first type heavily doped region.Type: GrantFiled: August 2, 2010Date of Patent: October 8, 2013Assignee: Amazing Microelectronics Corp.Inventors: Kun-Hsien Lin, Zi-Ping Chen, Che-Hao Chuang, Ryan Hsin-Chin Jiang
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Publication number: 20130221834Abstract: The present invention discloses a semiconductor-based planar micro-tube discharger structure and a method for fabricating the same. The method comprises steps: forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap; forming an insulating layer over the patterned electrodes and the separating block and filling the insulating layer into the gap. Thereby are formed at least two discharge paths. The method can fabricate a plurality discharge paths in a semiconductor structure. Therefore, the structure of the present invention has very high reliability and reusability.Type: ApplicationFiled: May 4, 2012Publication date: August 29, 2013Inventors: Tung-Yang Chen, Ming-Dou Ker, Ryan Hsin-Chin Jiang
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Publication number: 20130153957Abstract: A silicon-controlled-rectifier (SCR) with adjustable holding voltage is disclosed, which comprises a heavily doped semiconductor layer and an epitaxial layer formed on the heavily doped semiconductor layer. A first N-well having a first P-heavily doped area is formed in the epitaxial layer. A second N-well or a first P-well is formed in the epitaxial layer. When the second N-well is formed in the epitaxial layer, a P-doped area is located between the first N-well and the second N-well. Besides, a first N-heavily doped area is formed in the second N-well or the first P-well. At least one deep isolation trench is formed in the epitaxial layer and located between the first P-heavily doped area and the first N-heavily doped area. A distance between the deep isolation trench and the heavily doped semiconductor layer is larger than zero.Type: ApplicationFiled: December 20, 2011Publication date: June 20, 2013Inventors: Kun-Hsien Lin, Che-Hao Chuang, Ryan Hsin-Chin Jiang
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Publication number: 20130127007Abstract: A transient voltage suppressor without leakage current is disclosed, which comprises a P-substrate. There is an N-type epitaxial layer formed on the P-substrate, and a first N-heavily doped area, a first P-heavily doped area, an electrostatic discharge (ESD) device and at least one deep isolation trench are formed in the N-epitaxial layer. A first N-buried area is formed in the bottom of the N-epitaxial layer to neighbor the P-substrate and located below the first N-heavily doped area and the first P-heavily doped area. The ESD device is coupled to the first N-heavily doped area. The deep isolation trench is not only adjacent to the first N-heavily doped area, but has a depth greater than a depth of the first N-buried area, thereby separating the first N-buried area and the ESD device.Type: ApplicationFiled: November 23, 2011Publication date: May 23, 2013Inventors: Che-Hao Chuang, Kun-Hsien Lin, Ryan Hsin-Chin Jiang
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Patent number: 8431999Abstract: A low capacitance transient voltage suppressor is disclosed. The suppressor comprises an N-type heavily doped substrate and an epitaxial layer formed on the substrate. At least one steering diode structure formed in the epitaxial layer comprises a diode lightly doped well and a first P-type lightly doped well, wherein a P-type heavily doped area is formed in the diode lightly doped well and a first N-type heavily doped area and a second P-type heavily doped area are formed in the first P-type lightly doped well. A second P-type lightly doped well having two N-type heavily doped areas is formed in the epitaxial layer. In addition, an N-type heavily doped well and at least one deep isolation trench are formed in the epitaxial layer, wherein the trench has a depth greater than or equal to depths of all the doped wells, so as to separate at least one doped well.Type: GrantFiled: March 25, 2011Date of Patent: April 30, 2013Assignee: Amazing Microelectronic Corp.Inventors: Yu-Shu Shen, Kun-Hsien Lin, Che-Hao Chuang, Ryan Hsin-Chin Jiang
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Publication number: 20130003242Abstract: A transient voltage suppressor (TVS) for multiple pin assignments is disclosed. The suppressor comprises at least two cascade-diode circuits in parallel to each other and an electrostatic-discharge clamp element in parallel to each cascade-diode circuit and connected with a low voltage. One cascade-diode circuit is connected with a high voltage, and the other cascade-diode circuits are respectively connected with I/O pins. Each cascade-diode circuit further comprises a first diode and a second diode cascaded to the first diode, wherein a node between the first diode and the second diode is connected with the high voltage or the one I/O pin. The design of the present invention can meet several bounding requirements. It is flexible different pin assignments of TVS parts.Type: ApplicationFiled: September 12, 2012Publication date: January 3, 2013Inventors: Kun-Hsien LIN, Che-Hao Chuang, Ryan Hsin-Chin Jiang
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Patent number: 8304838Abstract: An electrostatic discharge protection device structure is disclosed, which comprises a semiconductor substrate and an N-type epitaxial layer arranged on the semiconductor substrate. At least one snapback cascade structure is arranged in the N-type epitaxial layer, wherein the snapback cascade structure further comprises first and second P-type wells arranged in the N-type epitaxial layer. First and second heavily doped areas arranged in the first P-type well respectively belong to opposite types. And, third and fourth heavily doped areas arranged in the second P-type well respectively belong to opposite types, wherein the second and third heavily doped areas respectively belong to opposite types and are electrically connected with each other. When the first heavily doped area receives an ESD signal, an ESD current flows from the first heavily doped area to the fourth heavily doped area through the first P-type well, the N-type epitaxial layer, and the second P-type well.Type: GrantFiled: August 23, 2011Date of Patent: November 6, 2012Assignee: Amazing Microelectronics Corp.Inventors: Zi-Ping Chen, Tung-Yang Chen, Kun-Hsien Lin, Ryan Hsin-Chin Jiang
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Publication number: 20120241903Abstract: A low capacitance transient voltage suppressor is disclosed. The suppressor comprises an N-type heavily doped substrate and an epitaxial layer formed on the substrate. At least one steering diode structure formed in the epitaxial layer comprises a diode lightly doped well and a first P-type lightly doped well, wherein a P-type heavily doped area is formed in the diode lightly doped well and a first N-type heavily doped area and a second P-type heavily doped area are formed in the first P-type lightly doped well. A second P-type lightly doped well having two N-type heavily doped areas is formed in the epitaxial layer. In addition, an N-type heavily doped well and at least one deep isolation trench are formed in the epitaxial layer, wherein the trench has a depth greater than or equal to depths of all the doped wells, so as to separate at least one doped well.Type: ApplicationFiled: March 25, 2011Publication date: September 27, 2012Inventors: Yu-Shu SHEN, Kun-Hsien Lin, Che-Hao Chuang, Ryan Hsin-Chin Jiang
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Patent number: 8237193Abstract: A lateral transient voltage suppressor for low-voltage applications. The suppressor includes an N-type heavily doped substrate and at least two clamp diode structures horizontally arranged in the N-type heavily doped substrate. Each clamp diode structure further includes a clamp well arranged in the N-type heavily doped substrate and having a first heavily doped area and a second heavily doped area. The first and second heavily doped areas respectively belong to opposite conductivity types. There is a plurality of deep isolation trenches arranged in the N-type heavily doped substrate and having a depth greater than depth of the clamp well. The deep isolation trenches can separate each clamp well. The present invention avoids the huge leakage current to be suitable for low-voltage application.Type: GrantFiled: July 15, 2010Date of Patent: August 7, 2012Assignee: Amazing Microelectronic Corp.Inventors: Che-Hao Chuang, Kun-Hsien Lin, Ryan Hsin-Chin Jiang