Structure and method to prevent over erasure of nonvolatile memory transistors
A method and structure for preventing over erasure in non-volatile memory cells uses simultaneous erase and program current injections which offset one another. These currents come from two separate injection points within the non-volatile memory transistor and are dominant at different points during the erase operation. The first occurring current erases the non-volatile device and the second prevents over erasure.
Latest NVX Corporation Patents:
- Semiconductor non-volatile latch device including embedded non-volatile elements
- Single poly memory cell and array
- Integrated circuit timer function using natural decay of charge stored in a dielectric
- Flash memory system, and methods of constructing and utilizing same
- Flash memory system, and methods of constructing and utilizing same
Claims
1. A non-volatile integrated memory device, comprising:
- a semiconductor substrate;
- a memory transistor in said substrate, said memory transistor having an electrically alterable threshold voltage, said memory transistor having a source region, a drain region, a channel region between said source and drain regions in said substrate, a gate, and a charge storage layer between at least portions of said gate and said substrate;
- means for simultaneously injecting charge into said charge storage layer from at least a first node and a second node during a write operation in which the threshold voltage of said memory transistor is charged;
- and means for setting current flows from said first and second nodes to be substantially equal in magnitude when a predetermined value is achieved during the write operation.
2. The device according to claim 1 wherein at least one of said nodes provides current by quantum mechanical tunneling.
3. The device according to claim 1 wherein said means for setting the current flow from said nodes comprises at least means for controlling an externally applied voltage to create an electric field and the electric field created by the accumulated charge in said charge storage layer to control the current from said first and second nodes.
4. The device according to claim 3 wherein said means to set current flow further comprises means for decreasing the magnitude of current from said first node and to simultaneously increase the magnitude of current from said second node as said accumulated charge increases.
5. The device according to claim 3 wherein said externally applied voltage is applied between said gate and said substrate.
6. The device according to claim 1 wherein said first node comprises said memory transistor channel.
7. The device according to claim 1 wherein said second node comprises said memory transistor gate.
8. The device according to claim 1 further comprising a bottom tunnel oxide between said substrate and said charge storage layer and a top blocking dielectric between said gate and said charge storage layer.
9. The device according to claim 8 wherein said charge storage layer comprises silicon nitride and said top blocking dielectric comprises a layer of silicon dioxide.
10. The device according to claim 8 wherein said charge storage layer comprises a floating gate of conductive material.
11. The device according to claim 8 wherein said top blocking dielectric is a three layer composite structure of silicon dioxide, silicon nitride, and silicon dioxide.
12. The device according to claim 1 wherein said memory transistor is a SONOS tunneling metal insulator semiconductor field effect transistor.
13. The device according to claim 1 wherein said charge storage layer comprises silicon oxynitride.
14. The device according to claim 1 wherein said charge storage layer comprises a floating gate of conductive material.
15. The device according to claim 1 wherein said substrate has a first conductivity type and said source and drain regions have a second conductivity type.
16. A method for preventing over erasure in a non-volatile memory cell, comprising:
- injecting a first current into the memory cell to erase the memory cell during an erase operation;
- injecting a second current into the memory cell, wherein said second current is injected during at least a period of time when said first current is injected, to prevent over erasure of the cell during the erase operation.
17. The method of claim 16 further comprising adjusting said first and second currents to offset one another.
18. The method of claim 16 wherein said first and second currents are injected from respective separate injection nodes.
19. The method of claim 16 wherein said first and second currents are respectively dominant at different periods of time during the write operation.
20. The devices of claim 1 wherein said write operation comprises an erase operation.
21. The device of claim 1 wherein said write operation comprises a program operation.
22. The device of claim 1 wherein said predetermined value is an erased state threshold voltage.
23. The device of claim 1 wherein said predetermined value is a programmed state threshold voltage.
24. A method for preventing over-writing a non-volatile memory cell during a write operation, wherein said write operation purposely changes the threshold voltage of a non-volatile transistor within said non-volatile memory cell, and wherein said over-writing inadvertently results when said threshold voltage changes to a value beyond a predetermined level, comprising:
- injecting a first current into said non-volatile memory cell to purposely change said threshold voltage during a write operation;
- injecting a second current into said non-volatile memory cell to prevent over-writing said non-volatile memory cell;
- accumulating charge from said first and second currents within said non-volatile memory cell; and
- utilizing said accumulating charge to create an electric field that constrains changes in said first and second currents when they achieve respective predetermined levels.
25. The method according to claim 24 wherein said write operation comprises an erase operation.
26. The method according to claim 24 wherein said write operation comprises a program operation.
27. The method according to claim 24 wherein said non-volatile transistor comprises a floating-gate non-volatile field effect transistor.
28. The method according to claim 24 wherein said non-volatile memory transistor comprises a SONOS non-volatile field effect transistor.
29. The method according to claim 24 wherein said first and second currents are injected from respective separate injection nodes.
30. The method according to claim 24 wherein said first and second currents are respectively dominant at different periods of time during the write operation.
31. The method according to claim 24 wherein said respective predetermined levels for said first and second currents constitute values that are substantially equal in magnitude.
32. The method according to claim 24 wherein said first current is injected through the channel of said non-volatile memory transistor.
33. The method according to claim 24 wherein said second current is injected through the gate of said non-volatile memory transistor.
| 5327385 | July 5, 1994 | Oyama |
| 5477485 | December 19, 1995 | Bergemont et al. |
| 5586073 | December 17, 1996 | Hiura et al. |
| WO 94/10686(A1) | May 1994 | WOX |
- Miyawaki et al. "A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16-Mb/64-Mb Flash Memories", IEEE Jour. Solid-State Circuits, vol. 27, No. 4, Apr. 1992 pp. 583-588. Momodomi et al., "An Experimental 4-Mbit CMOS EEPROM with a NAND-Structured Cell", IEEE Jour. Solid-State Circuits, vol. 24, No. 5, Oct. 1989 pp. 1238-1243. Lundstrom, et al., "Properties of MNOS Structures", IEEE Jour. Solid-State Circuits, vol. ED-19, No. 6, Jun. 1972 pp. 826-836. Nozaki, et al., "A -1Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application", IEEE Jour. Solid-State Circuits, vol. 26, No. 4, Apr., 1991 pp. 497-501. Suzuki, et al., "A Low Voltage Alterable EEPROM with Metal-Oxide-Nitride-Oxide Semiconductor (MONOS) Structures", IEEE Jour. Solid-State Circuits, vol. ED-30, No. 2, Feb., 1983. Svensson et al., "Trap-assisted charge injection in MNOS structures", J. Appl. Phys, vol. 44, No. 10, Oct. 1973 pp. 46574663. Sze, Physics of Semiconductor Devices, Wiley-Interscience, 1969, pp. 425-437.
Type: Grant
Filed: Dec 23, 1996
Date of Patent: Jun 30, 1998
Assignee: NVX Corporation (Colorado Springs, CO)
Inventors: Loren T. Lancaster (Colorado Springs, CO), Ryan T. Hirose (Colorado Springs, CO)
Primary Examiner: Vu A. Le
Attorney: Richard A. Holland & Hart LLP Bachand
Application Number: 8/772,970
International Classification: G11C 1140;
