Patents by Inventor Ryo Hayashi

Ryo Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8502222
    Abstract: An amorphous oxide semiconductor contains at least one element selected from In, Ga, and Zn at an atomic ratio of InxGayZnz, wherein the density M of the amorphous oxide semiconductor is represented by the relational expression (1) below: M?0.94×(7.121x+5.941y+5.675z)/(x+y+z)??(1) where 0?x?1, 0?y?1, 0?z?1, and x+y+z?0.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: August 6, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hisato Yabuta, Ayanori Endo, Nobuyuki Kaji, Ryo Hayashi
  • Patent number: 8487266
    Abstract: An X-ray detector includes an X-ray photoelectric conversion layer configured to produce electric charges in proportion to X-ray irradiation incident on the layer, a collecting electrode configured to collect the electric charges produced by the X-ray photoelectric conversion layer, a common electrode disposed on a surface of the X-ray photoelectric conversion layer opposite to the collecting electrode, a storage capacitor configured to store the electric charges collected by the collecting electrode, and a readout unit configured to read out the electric charges stored in the storage capacitor. A voltage is to be applied between the collecting electrode and the common electrode. The X-ray photoelectric conversion layer is formed of a polycrystalline oxide.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: July 16, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hisato Yabuta, Nobuyuki Kaji, Ryo Hayashi, Masatoshi Watanabe, Taihei Mukaide, Kazunori Fukuda
  • Patent number: 8445902
    Abstract: Provided are a coplanar structure thin film transistor that allows a threshold voltage to change only a little under electric stress, and a method of manufacturing the same. The thin film transistor includes on a substrate at least: a gate electrode; a gate insulating layer; an oxide semiconductor layer including a source electrode, a drain electrode, and a channel region; a channel protection layer; and an interlayer insulating layer. The channel protection layer includes one or more layers, the layer in contact with the oxide semiconductor layer among the one or more layers being made of an insulating material containing oxygen, ends of the channel protection layer are thinner than a central part of the channel protection layer, the interlayer insulating layer contains hydrogen, and regions of the oxide semiconductor layer that are in direct contact with the interlayer insulating layer form the source electrode and the drain electrode.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: May 21, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ayumu Sato, Ryo Hayashi, Hisato Yabuta, Masafumi Sano
  • Patent number: 8436349
    Abstract: In a process for fabricating a thin-film transistor in which a gate electrode 4 is to be formed on a substrate 1, the process has the steps of forming the gate electrode 4 on the substrate 1, forming a metal oxide layer 7 in such a way as to cover the gate electrode 4, forming a source electrode 6 and a drain electrode 5, and carrying out annealing in an inert gas to change part of the metal oxide layer 7 into a channel region.
    Type: Grant
    Filed: February 18, 2008
    Date of Patent: May 7, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masafumi Sano, Ryo Hayashi
  • Patent number: 8426243
    Abstract: There is provided an amorphous oxide semiconductor including hydrogen and at least one element of indium (In) and zinc (Zn), the amorphous oxide semiconductor containing one of hydrogen atoms and deuterium atoms of 1×1020 cm?3 or more to 1×1022 cm?3 or less, and a density of bonds between oxygen and hydrogen except bonds between excess oxygen (OEX) and hydrogen in the amorphous oxide semiconductor being 1×1018 cm?3 or less.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: April 23, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ryo Hayashi, Hideyuki Omura, Hideya Kumomi, Yuzo Shigesato
  • Publication number: 20130096092
    Abstract: Disclosed are inhibitors of retroviral growth of formula (I), that are useful in treatment of retroviral infections such as HIV. Also disclosed are a composition comprising a pharmaceutically acceptable carrier and at least one compound or salt of the invention, a method for inactivating a virus, a method for dissociating a metal ion from a zinc finger-containing protein, and a method for inhibiting the transmission of a virus.
    Type: Application
    Filed: June 10, 2011
    Publication date: April 18, 2013
    Applicants: Health and Human Services
    Inventors: Daniel Appella, Ettore Appella, John K. Inman, Lisa M. Miller Jenkins, Ryo Hayashi, Deyun Wang
  • Patent number: 8415198
    Abstract: A production method of a thin film transistor including an active layer including an amorphous oxide semiconductor film, wherein a step of forming the active layer includes a first step of forming the oxide film in an atmosphere having an introduced oxygen partial pressure of 1×10?3 Pa or less, and a second step of annealing the oxide film in an oxidative atmosphere after the first step.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: April 9, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Naho Itagaki, Toru Den, Nobuyuki Kaji, Ryo Hayashi, Masafumi Sano
  • Patent number: 8389996
    Abstract: A method for forming a SnO-containing semiconductor film includes a first step of forming a SnO-containing film; a second step of forming an insulator film composed of an oxide or a nitride on the SnO-containing film to provide a laminated film including the SnO-containing film and the insulator film; and a third step of subjecting the laminated film to a heat treatment.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: March 5, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hisato Yabuta, Nobuyuki Kaji, Ryo Hayashi
  • Patent number: 8344373
    Abstract: To achieve, in an oxide semiconductor thin layer transistor, both the stability of threshold voltage against electric stress and suppression of variation in the threshold voltage in a transfer characteristic. A thin film transistor includes an oxide semiconductor layer and a gate insulating layer disposed so as to be in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer contains hydrogen atoms and includes at least two regions that function as active layers of the oxide semiconductor and have different average hydrogen concentrations in the layer thickness direction; and when the regions functioning as the active layers of the oxide semiconductor are sequentially defined as, from the side of the gate insulating layer, a first region and a second region, the average hydrogen concentration of the first region is lower than the average hydrogen concentration of the second region.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: January 1, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ayumu Sato, Hideya Kumomi, Ryo Hayashi, Tomohiro Watanabe
  • Publication number: 20120282742
    Abstract: A method for manufacturing a silicon semiconductor device includes the steps of diluting a silicon-containing raw material gas with hydrogen gas by a factor equal to or larger than 600, applying radiofrequency power to a gas mixture of the diluted raw material gas and hydrogen gas to induce electric discharge, depositing silicon out of the raw material gas decomposed by the electric discharge onto a substrate, and controlling the pressure of the gas mixture to be equal to or higher than 600 Pa. The power density Pw(W/cm2) of the radiofrequency power is specified in such a manner that the value Pw(W/cm2)*D/P(Pa) should fall within the range of 0.083 to 0.222, both inclusive, where D represents the dilution factor between the raw material gas and hydrogen gas and P (Pa) represents the pressure of the gas mixture.
    Type: Application
    Filed: July 17, 2012
    Publication date: November 8, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Koichi Matsuda, Ryo Hayashi, Shinji Kodaira
  • Patent number: 8304298
    Abstract: To provide an enhancement-depletion (E/D) inverter which can be easily manufactured, in the present invention, a method of manufacturing an inverter which is composed of an oxide semiconductor in which a channel layer includes at least one element selected from In, Ga and Zn formed on a same substrate, the inverter being the E/D inverter having plural thin film transistors, is characterized by comprising the steps of: forming a first transistor and a second transistor, the thicknesses of the channel layers of the first and second transistors being mutually different; and executing heat treatment to at least one of the channel layers of the first and second transistors.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: November 6, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masato Ofuji, Katsumi Abe, Ryo Hayashi, Masafumi Sano, Hideya Kumomi
  • Patent number: 8216879
    Abstract: A method for manufacturing a semiconductor device or apparatus having at least a semiconductor as a component, characterized by including irradiating the semiconductor with light having a longer wavelength than the absorption edge wavelength of the semiconductor to change the threshold voltage of the semiconductor device or apparatus, and checking the threshold voltage of the semiconductor device or apparatus, after or during irradiation with the light, to determine whether the threshold voltage is in a predetermined range, during manufacturing the semiconductor device or apparatus.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: July 10, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuyuki Kaji, Masato Ofuji, Yasuyoshi Takai, Takehiko Kawasaki, Norio Kaneko, Ryo Hayashi
  • Publication number: 20120168750
    Abstract: Provided is a bottom gate type thin film transistor including on a substrate (1) a gate electrode (2), a first insulating film (3) as a gate insulating film, an oxide semiconductor layer (4) as a channel layer, a second insulating film (5) as a protective layer, a source electrode (6), and a drain electrode (7), in which the oxide semiconductor layer (4) includes an oxide including at least one selected from the group consisting of In, Zn, and Sn, and the second insulating film (5) includes an amorphous oxide insulator formed so as to be in contact with the oxide semiconductor layer (4) and contains therein 3.8×1019 molecules/cm3 or more of a desorbed gas observed as oxygen by temperature programmed desorption mass spectrometry.
    Type: Application
    Filed: March 13, 2012
    Publication date: July 5, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Ryo Hayashi, Nobuyuki Kaji, Hisato Yabuta
  • Patent number: 8207531
    Abstract: Provided is a thin film transistor including: a first gate electrode; a first gate insulating layer covering the first gate electrode; a semiconductor layer on the first gate insulating layer; a second gate insulating layer on the semiconductor layer; a second gate electrode on the second gate insulating layer; and a drain electrode and a source electrode electrically connected to the semiconductor layer, in which: the semiconductor layer is an amorphous oxide semiconductor containing at least one of Zn, Ga, In, and Sn; the first gate electrode shields light entering the semiconductor layer from below, and the second gate electrode shields light entering the semiconductor layer from above; and the second gate electrode is electrically connected to the first gate electrode by penetrating the first gate insulating layer and the second gate insulating layer, to thereby shield light entering the semiconductor layer from at least one of sides thereof.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: June 26, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Takahashi, Ryo Hayashi, Seiichiro Yaginuma
  • Publication number: 20120153277
    Abstract: A channel layer is formed on a substrate by using an oxide semiconductor and then a sacrificial layer of an oxide containing In, Zn and Ga and representing an etching rate greater than the etching rate of the oxide semiconductor is formed on the channel layer. Thereafter, a source electrode and a drain electrode are formed on the sacrificial layer and the sacrificial layer exposed between the source electrode and the drain electrode is removed by means of wet etching.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 21, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Seiichiro Yaginuma, Tatsuya Iwasaki, Ryo Hayashi, Hideya Kumomi, Masaya Watanabe
  • Publication number: 20120146021
    Abstract: An amorphous oxide semiconductor contains at least one element selected from In, Ga, and Zn at an atomic ratio of InxGayZnz, wherein the density M of the amorphous oxide semiconductor is represented by the relational expression (1) below: M?0.94×(7.121x+5.941y+5.675z)/(x+y+z) ??(1) where 0?x?1, 0?y?1, 0?z?1, and x+y+z?0.
    Type: Application
    Filed: February 23, 2012
    Publication date: June 14, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hisato Yabuta, Ayanori Endo, Nobuyuki Kaji, Ryo Hayashi
  • Patent number: 8193045
    Abstract: A manufacturing method of a thin film transistor having at least a gate electrode, a gate insulation film, an oxide semiconductor layer, a first insulation film, a source electrode, a drain electrode, and a second insulation film on a substrate, including: forming the gate electrode on the substrate; forming the gate insulation film on the gate electrode; forming a semiconductor layer including amorphous oxide on the gate insulation film; patterning the gate insulation film; patterning the oxide semiconductor layer; reducing the oxide semiconductor layer in resistance by forming the first insulation film on the oxide semiconductor layer in the atmosphere not including an oxidized gas; patterning the first insulation film and forming a contact hole between the source electrode and the drain electrode and the oxide semiconductor layer; forming a source electrode layer and a drain electrode layer in the oxide semiconductor layer through the contact hole; forming the source electrode and the drain electrode throu
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: June 5, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideyuki Omura, Ryo Hayashi
  • Publication number: 20120132911
    Abstract: A transistor is constituted of a gate electrode 2, a gate insulation layer 3, a semiconductor layer 4 formed of an amorphous oxide, a source electrode 5, a drain electrode 6 and a protective layer 7. The protective layer 7 is provided on the semiconductor layer 4 in contact with the semiconductor layer 4, and the semiconductor layer 4 includes a first layer at least functioning as a channel layer and a second layer having higher resistance than the first layer. The first layer is provided on the gate electrode 2 side of the semiconductor layer 4 and the second layer is provided on the protective layer 7 side of the semiconductor layer 4.
    Type: Application
    Filed: February 9, 2012
    Publication date: May 31, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Mikio Shimada, Ryo Hayashi, Hideya Kumomi
  • Publication number: 20120115276
    Abstract: There is provided an amorphous oxide semiconductor including hydrogen and at least one element of indium (In) and zinc (Zn), the amorphous oxide semiconductor containing one of hydrogen atoms and deuterium atoms of 1×1020 cm?3 or more to 1×1022 cm?3 or less, and a density of bonds between oxygen and hydrogen except bonds between excess oxygen (OEX) and hydrogen in the amorphous oxide semiconductor being 1×1018 cm?3 or less.
    Type: Application
    Filed: January 18, 2012
    Publication date: May 10, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: RYO HAYASHI, HIDEYUKI OMURA, HIDEYA KUMOMI, YUZO SHIGESATO
  • Patent number: 8154017
    Abstract: An amorphous oxide semiconductor contains at least one element selected from In, Ga, and Zn at an atomic ratio of InxGayZnz, wherein the density M of the amorphous oxide semiconductor is represented by the relational expression (1) below: M?0.94×(7.121x+5.941y+5.675z)/(x+y+z)??(1) where 0?x?1, 0?y?1, 0?z?1, and x+y+z?0.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: April 10, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hisato Yabuta, Ayanori Endo, Nobuyuki Kaji, Ryo Hayashi