Patents by Inventor Ryo Nagai
Ryo Nagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090049749Abstract: A hydrogen generating material of the present invention includes a metal material that reacts with water to generate hydrogen, and a heat generating material that reacts with water to generate heat and is a material other than the metal material. The heat generating material is unevenly distributed with respect to the metal material. The hydrogen generating material has a plurality of regions that differ in content of the heat generating material. The content of the heat generating material is preferably 30 wt % to 80 wt % in a region with the highest content of the heat generating material. A hydrogen generator of the present invention includes the hydrogen generating material and a vessel containing the hydrogen generating material. The vessel can accommodate another inner vessel.Type: ApplicationFiled: August 9, 2006Publication date: February 26, 2009Inventors: Takeshi Miki, Toshihiro Nakai, Ryo Nagai, Shoji Saibara
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Publication number: 20080237752Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: ApplicationFiled: May 29, 2008Publication date: October 2, 2008Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Patent number: 7417291Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: GrantFiled: April 18, 2007Date of Patent: August 26, 2008Assignee: Elpida Memory, Inc.Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Patent number: 7414291Abstract: A method includes the steps of: implanting boron into a surface region of a silicon substrate to form a p+ diffused region; implanting indium into the surface of the p+ diffused region, to form an indium-implanted layer; forming a contact metal layer on the indium-implanted layer; and reacting silicon in the silicon substrate including the indium-implanted layer with metal in the contact metal layer to form a titanium silicide layer.Type: GrantFiled: April 6, 2005Date of Patent: August 19, 2008Assignee: Elpida Memory, Inc.Inventors: Shigetomi Michimata, Ryo Nagai, Satoru Yamada, Yoshitaka Nakamura, Ryoichi Nakamura
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Publication number: 20070241400Abstract: A high performance semiconductor device has an NMOS and a PMOS for which each channel is formed on an optimal crystal plane. A semiconductor device comprises a silicon single-crystal substrate whose surface is a (110) crystal plane, a PMOSFET formed on a (110) plane as a wall surface of a Fin perpendicular to a <110> axis, and an NMOSFET formed on a (001) plane as a wall surface of a Fin perpendicular to a <001> axis on the (110) plane of the substrate.Type: ApplicationFiled: April 9, 2007Publication date: October 18, 2007Applicant: Elpida Memory, Inc.Inventor: Ryo NAGAI
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Publication number: 20070187783Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: ApplicationFiled: April 18, 2007Publication date: August 16, 2007Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Patent number: 7224034Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: GrantFiled: November 2, 2004Date of Patent: May 29, 2007Assignee: Elpida Memory, Inc.Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Publication number: 20070031094Abstract: An optical fiber cable has: a cable portion having an optical fiber tape core wire that a plurality of optical fiber core wires are stacked in parallel, and a cable sheath formed on the plurality of optical fiber core wires; and mold-releasing sheets disposed in parallel with the optical fiber tape core wire. The mold-releasing sheets have an end portion extended from the end of the optical fiber tape core wire. An end of the optical fiber tape core wire is covered by the end portion of the mold-releasing sheet.Type: ApplicationFiled: July 27, 2006Publication date: February 8, 2007Applicant: HITACHI CABLE, LTD.Inventors: Misao Watahiki, Ryo Nagai, Takahiro Sato
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Publication number: 20060171645Abstract: An optical fiber cable in which an optical fiber tape unit can be taken out easily from a sheath is disclosed. An optical fiber cable having a substantially rectangular cross section has one or more optical fiber tape units, a sheath for accommodating the optical fiber tape units, the sheath being of a substantially rectangular cross section, a first pair of notches formed at long sides of the cross section of the sheath, a first line connecting the first pair of notches being across the optical fiber tape units, and second and third pairs of notches formed at the long sides and above and below the first pair of notches, second and third lines connecting the second and third pairs of notches not being across the optical fiber tape units.Type: ApplicationFiled: January 3, 2006Publication date: August 3, 2006Applicant: Hitachi Cable, Ltd.Inventors: Yoshihiro Kodaka, Takahiro Sato, Ryo Nagai
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Publication number: 20060131622Abstract: A CMOS device includes a silicon substrate, a gate insulating film, and a gate electrode including a silicon layer doped with boron and phosphorous, a tungsten nitride layer and a tungsten layer. A ratio of a maximum boron concentration to a minimum boron concentration in a boron concentration profile across the thickness of the silicon layer is not higher than 100. The CMOS device has a lower NBTI (Negative Bias Temperature Instability) degradation.Type: ApplicationFiled: December 13, 2005Publication date: June 22, 2006Applicant: Elpida Memory, Inc.Inventors: Satoru Yamada, Ryo Nagai
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Patent number: 7057243Abstract: In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.Type: GrantFiled: August 27, 2003Date of Patent: June 6, 2006Assignees: Elpida Memory, Inc., Hitachi, Ltd.Inventors: Satoru Yamada, Ryo Nagai, Kiyonori Oyu, Ryoichi Nakamura, Norikatsu Takaura
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Publication number: 20050230712Abstract: A method includes the steps of: implanting boron into a surface region of a silicon substrate to form a p+ diffused region; implanting indium into the surface of the p+ diffused region, to form an indium-implanted layer; forming a contact metal layer on the indium-implanted layer; and reacting silicon in the silicon substrate including the indium-implanted layer with metal in the contact metal layer to form a titanium silicide layer.Type: ApplicationFiled: April 6, 2005Publication date: October 20, 2005Inventors: Shigetomi Michimata, Ryo Nagai, Satoru Yamada, Yoshitaka Nakamura, Ryoichi Nakamura
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Publication number: 20050208716Abstract: A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved. Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each gate electrode and a sidewall film on the sidewall thereof are formed of a silicon oxide film. A polycrystalline silicon film formed on the gate electrodes and between the gate electrodes is polished by a CMP method, and thereby contact electrodes are formed. Also, sidewall films each composed of a laminated film of the silicon oxide film and the polycrystalline silicon film are formed on the sidewall of the gate electrodes in the logic circuit area, and these films are used as a mask to form semiconductor areas. As a result, it is possible to reduce the boron penetration and form contact electrodes in a self-alignment manner. In addition, the performance of the MISFET constituting the logic circuit can be improved.Type: ApplicationFiled: May 17, 2005Publication date: September 22, 2005Inventors: Norikatsu Takaura, Hideyuki Matsuoka, Shinichiro Kimura, Ryo Nagai, Satoru Yamada
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Patent number: 6905794Abstract: An air-hydrogen battery with high energy density and satisfactory cycle characteristics is provided. The air-hydrogen battery includes: a positive electrode made of an air electrode; a negative electrode provided with a hydrogen-absorbing alloy; and a cation-exchange film or an anion-exchange film formed as an electrolyte between the positive electrode and the negative electrode, wherein a periphery of the hydrogen-absorbing alloy of the negative electrode is covered with an anion-exchange resin, whereby the contact area between the anion-exchange resin that functions as an electrolyte and the hydrogen-absorbing alloy is increased, and the utilization factor and resistance to corrosion of the hydrogen-absorbing alloy are enhanced.Type: GrantFiled: August 16, 2001Date of Patent: June 14, 2005Assignee: Hitachi Maxell, Ltd.Inventors: Hiroshi Kashino, Yasuo Arishima, Shinsuke Shibata, Gun Seki, Ryo Nagai
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Patent number: 6900492Abstract: A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved. Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each gate electrode and a sidewall film on the sidewall thereof are formed of a silicon oxide film. A polycrystalline silicon film formed on the gate electrodes and between the gate electrodes is polished by a CMP method, and thereby contact electrodes are formed. Also, sidewall films each composed of a laminated film of the silicon oxide film and the polycrystalline silicon film are formed on the sidewall of the gate electrodes in the logic circuit area, and these films are used as a mask to form semiconductor areas. As a result, it is possible to reduce the boron penetration and form contact electrodes in a self-alignment manner. In addition, the performance of the MISFET constituting the logic circuit can be improved.Type: GrantFiled: June 7, 2002Date of Patent: May 31, 2005Assignees: Hitachi, Ltd., NEC Corporation, NEC Electronics CorporationInventors: Norikatsu Takaura, Hideyuki Matsuoka, Shinichiro Kimura, Ryo Nagai, Satoru Yamada
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Publication number: 20050100773Abstract: A liquid fuel cell comprising a plurality of unit fuel cells each having a positive electrode (8) for reducing oxygen, a negative electrode (9) for oxidizing liquid fuel, and an electrolyte layer (10) interposed between the positive electrode (8) and the negative electrode (9), and a section (3) for storing liquid fuel (4), wherein power can be generated stably while reducing the size by arranging the plurality of unit fuel cells on the substantially same plane. Each electrolyte layer of the unit fuel cell preferably constitutes a continuous integrated electrolyte layer.Type: ApplicationFiled: February 14, 2003Publication date: May 12, 2005Inventors: Hiroshi Kashino, Yasuo Arishima, Shinsuke Shibata, Gun Seki, Shoji Saibara, Ryo Nagai
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Publication number: 20050087880Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: ApplicationFiled: November 2, 2004Publication date: April 28, 2005Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Publication number: 20050035428Abstract: A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4-L5), (L6-L5), and (L4-L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.Type: ApplicationFiled: September 22, 2004Publication date: February 17, 2005Inventors: Norikatsu Takaura, Riichiro Takemura, Hideyuki Matsuoka, Shinichiro Kimura, Hisao Asakura, Ryo Nagai, Satoru Yamada
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Patent number: 6828242Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: GrantFiled: August 20, 2002Date of Patent: December 7, 2004Assignees: Hitachi, Ltd., NEC Corporation, NEC Electronics CorporationInventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Patent number: 6812540Abstract: A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4−L5), (L6−L5), and (L4−L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.Type: GrantFiled: November 19, 2002Date of Patent: November 2, 2004Assignees: Hitachi, Ltd., Elpida Memory, Inc.Inventors: Norikatsu Takaura, Riichiro Takemura, Hideyuki Matsuoka, Shinichiro Kimura, Hisao Asakura, Ryo Nagai, Satoru Yamada