Abstract: A DRAM of an open bit line structure has a cell area smaller than that of a DRAM of a folded bit line structure and is susceptible to noise. A conventional DRAM of an open bit line structure has a large bit line capacitance and is susceptible to noise or has a large cell area. There has been no DRAM of an open bit line structure having a small bit line capacitance, unsusceptible to noise and having a small cell area. The present invention forms capacitor lower electrode plug holes not aligned with bit lines to reduce bit line capacitance. Bit lines are formed in a small width, capacitor lower electrode plugs are dislocated from positions corresponding to the centers of the bit lines in directions away from the bit lines and the contacts are formed in a reduced diameter to avoid increasing the cell area. Thus a semiconductor storage device of an open bit line structure resistant to noise and having a small cell area is provided.

Abstract: In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.

Abstract: A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved.

Abstract: By eliminating a part of sulfur atoms of the polysulfide segment of the formula: —Sm— (m≧3) of an organic sulfur compound, a carbon polysulfide is synthesized, which comprises carbon and sulfur as constitutive elements and contains at least 67 wt. % of sulfur and at least 95 wt. % of carbon and sulfur in total, and which has a disulfide linkage formed by most of the sulfur atoms in the molecule and also has a highly uniform structure. A nonaqueous electrolytic battery which has a high capacity and shows a small decrease in capacity in association with cyclic charge and discharge is provided using this carbon polysulfide as an active material for the positive electrode.

Abstract: A DRAM of an open bit line structure has a cell area smaller than that of a DRAM of a folded bit line structure and is susceptible to noise. A conventional DRAM of an open bit line structure has a large bit line capacitance and is susceptible to noise or has a large cell area. There has been no DRAM of an open bit line structure having a small bit line capacitance, unsusceptible to noise and having a small cell area. The present invention forms capacitor lower electrode plug holes not aligned with bit lines to reduce bit line capacitance. Bit lines are formed in a small width, capacitor lower electrode plugs are dislocated from positions corresponding to the centers of the bit lines in directions away from the bit lines and the contacts are formed in a reduced diameter to avoid increasing the cell area. Thus a semiconductor storage device of an open bit line structure resistant to noise and having a small cell area is provided.

Abstract: A DRAM of an open bit line structure has a cell area smaller than that of a DRAM of a folded bit line structure and is susceptible to noise. A conventional DRAM of an open bit line structure has a large bit line capacitance and is susceptible to noise or has a large cell area. There has been no DRAM of an open bit line structure having a small bit line capacitance, unsusceptible to noise and having a small cell area. The present invention forms capacitor lower electrode plug holes not aligned with bit lines to reduce bit line capacitance. Bit lines are formed in a small width, capacitor lower electrode plugs are dislocated from positions corresponding to the centers of the bit lines in directions away from the bit lines and the contacts are formed in a reduced diameter to avoid increasing the cell area. Thus a semiconductor storage device of an open bit line structure resistant to noise and having a small cell area is provided.

Abstract: An air-hydrogen battery with high energy density and satisfactory cycle characteristics is provided.

Abstract: A nickel metal-hydride cell having a paste type nickel positive electrode containing nickel hydroxide and a cobalt conducting aid selected from the group consisting of metal cobalt and cobalt compounds, a negative electrode which comprises a hydrogen absorbing alloy having a composition of the formula: MmNi5−x+yMx in which Mm is a rare earth element, M is a metal element, 0<x<2, and −0.2<y<0.6, a separator interposed between two electrodes, and an alkaline electrolytic solution, where a ratio of C—H to C—Co(II) is 1.3 or less, wherein C—H is a quantity of electricity of a discharge reserve formed in the negative electrode, and C—Co(II) is a quantity of electricity necessary for reducing cobalt oxide in the positive electrode to cobalt(II) oxide.

Abstract: A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4-L5), (L6-L5), and (L4-L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.

Abstract: A polymer electrolyte comprising an electrolyte salt, a non-aqueous solvent and a polymer which comprises repeating units of the formulas: —(R1—O)n—, and —[CH (R2)—CH2—O]m— in which n≧0 and m≧0 provided that n+m≧5, R1 is a C1-C6 alkyl group, and R2 is a C1-C6 alkyl group or a benzyl group, and a urea structure.

Abstract: Providing a semiconductor device which lessen influence of the transistor threshold voltage deviation that is one of noise elements when the sense amplifiers are amplified, and which are capable of accurately sensing and amplifying micro signals having read from the memory cells in the sense amplifiers. In a DRAM chip, P+-type gate PMOSs of P+-type polysilicon gates each having a low impurity density of channel and N+-type gate NMOSs of N+-type polysilicon gates are used in a sense amplifier cross coupling section to further increase substrate voltages of the PMOSs and to decrease substrate voltages of the NMOS. For this reason, a deviation of threshold voltage caused by channel implantation is reduced, and a small signal generated on a data line at a read operation of a low-potential memory array is accurately sensed and amplified by a sense amplifier.

Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

Abstract: A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved.

Abstract: Providing a semiconductor device which lessen influence of the transistor threshold voltage deviation that is one of noise elements when the sense amplifiers are amplified, and which are capable of accurately sensing and amplifying micro signals having read from the memory cells in the sense amplifiers.

Abstract: Desired operating characteristics are obtained from an MISFET in which a p-type silicon gate electrode is used by preventing the leakage of boron into the channel region in the following way. N-type amorphous silicon 9n is formed by ion-implanting phosphorus into an amorphous silicon. Next, boron is ion-implanted in n-type amorphous silicon 9n to convert it into p-type amorphous silicon 9p. Amorphous silicon 9p is then crystallized. Finally, the gate electrode of the MISFET is constructed of the p-type polycrystalline silicon, which has been obtained in the above steps, and in which phosphorus and boron have been implanted.

Abstract: An interpolation circuit generates two-phase square wave signals PA and PB from two-phase sinusoidal wave outputs ØA and ØB supplied from a photoelectric encoder. A gate signal generator slices a primary origin signal ØZ supplied from the photoelectric encoder with a predetermined reference level VRef to generate a gate signal Z. A first counter begins to count position pulses generated from the two-phase square wave signals PA and PB when the gate signal Z becomes active. A count value of the first counter is divided by two when the gate signal Z becomes non-active and the divided value is preset into a second counter. The second counter counts the position pulses generated from the two-phase square wave signals PA and PB. A comparator feeds an output origin signal PZ when a count value of the second counter reaches a predetermined offset value N.

Abstract: This invention obtains desired operating characteristics from an MISFET in which a p-type silicon gate electrode is used by preventing the leakage of boron into the channel region in the following way. N-type amorphous silicon 9n is formed by ion-implanting phosphorus into an amorphous silicon. Next, boron is ion-implanted in n-type amorphous silicon 9n to convert it into p-type amorphous silicon 9p. Amorphous silicon 9p is then crystallized. Finally, the gate electrode of the MISFET is constructed of the p-type polycrystalline silicon, which has been obtained in the above steps, and in which phosphorus and boron have been implanted.

Abstract: By eliminating a part of sulfur atoms of the polysulfide segment of the formula: —Sm— (m≧3) of an organic sulfur compound, a carbon polysulfide is synthesized, which comprises carbon and sulfur as constitutive elements and contains at least 67 wt. % of sulfur and at least 95 wt. % of carbon and sulfur in total, and which has a disulfide linkage formed by most of the sulfur atoms in the molecule and also has a highly uniform structure. A nonaqueous electrolytic battery which has a high capacity and shows a small decrease in capacity in association with cyclic charge and discharge is provided using this carbon polysulfide as an active material for the positive electrode.

Abstract: A mask for etching a relatively thin gate insulating film formed in a gate insulating film forming region is formed by patterning a photoresist film, and the mask is used for introducing an impurity for adjusting the threshold voltages of n-channel field-effect transistors and p-channel field-effect transistors having the relatively thin gate insulating film into regions on the semiconductor substrate not covered with the mask.

Abstract: In a case where an impurity for suppressing the short channel effect of MISFETs is introduced into a semiconductor substrate obliquely to the principal surface thereof, gate electrodes adjacent to each other are arranged so that the impurity to be introduced in directions crossing the gate electrodes may not be introduced into the part of the semiconductor substrate lying between the gate electrodes, and the source region of the MISFETs is arranged in the part between the gate electrodes.