Patents by Inventor Ryohei GEJO

Ryohei GEJO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955477
    Abstract: A semiconductor device according to the embodiment includes: a transistor region including a first trench, a first gate electrode provided in the first trench, a second trench, a second gate electrode provided in the second trench, a third trench, and a third gate electrode provided in the third trench; a diode region including a fifth trench and a conductive layer provided in the fifth trench; a boundary region including a fourth trench and a fourth gate electrode provided in the fourth trench, the boundary region being provided between the transistor region and the diode region; a first electrode pad electrically connected to the first gate electrode; a second electrode pad electrically connected to the second gate electrode; and a third electrode pad electrically connected to the third gate electrode and the fourth gate electrode.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: April 9, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tomoko Matsudai, Yoko Iwakaji, Ryohei Gejo
  • Publication number: 20240088220
    Abstract: A semiconductor device of embodiments includes: a semiconductor layer having a first face and a second face; a first semiconductor region of a first conductive type in the semiconductor layer, in contact with the second face, and including a first portion having a first minimum width, a second portion having a second minimum width smaller than the first minimum width, and a third portion connecting the first portion and the second portion and having a third minimum width smaller than the second minimum width; a plurality of second semiconductor regions of a second conductive type in contact with the second face; a third semiconductor region of the second conductive type between the first semiconductor region and the first face; a fourth semiconductor region of the first conductive type; a fifth semiconductor region of the second conductive type; a gate electrode facing the fourth semiconductor region.
    Type: Application
    Filed: February 3, 2023
    Publication date: March 14, 2024
    Inventor: Ryohei GEJO
  • Publication number: 20240079448
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, a first conductive member, a semiconductor member, and an insulating member. The first electrode includes a first face. The second electrode includes a first conductive region and a first conductive portion. The first conductive portion is electrically connected to the first conductive region. The first conductive member is provided between the first face and the first conductive region. The semiconductor member is provided between the first face and the second electrode. The semiconductor member includes a first semiconductor region of a first conductive type, a second semiconductor region of a second conductive type, a third semiconductor region of the second conductive type, a fourth semiconductor region of the first conductive type, and a fifth semiconductor region of the first conductive type. The second semiconductor region is located between the third partial region and the third semiconductor region.
    Type: Application
    Filed: January 25, 2023
    Publication date: March 7, 2024
    Inventors: Yoko IWAKAJI, Keiko KAWAMURA, Ryohei GEJO, Kaori FUSE
  • Patent number: 11923851
    Abstract: According to one embodiment, a drive device includes a drive circuit configured to drive a semiconductor device. The semiconductor device includes first to fourth electrodes, a semiconductor member, and an insulating member. The semiconductor member includes first to fourth semiconductor region. The first semiconductor region includes first to third partial regions. The first semiconductor region is between the first electrode and the second semiconductor region. The third semiconductor region is between the first and second semiconductor regions. The fourth semiconductor region is between the first electrode and the first semiconductor region. The second electrode is electrically connected to the second semiconductor region. The first partial region is between the fourth semiconductor region and the third electrode. The second partial region is between the fourth semiconductor region and the fourth electrode.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: March 5, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tatsunori Sakano, Ryohei Gejo, Tomoko Matsudai
  • Publication number: 20240055386
    Abstract: According to one embodiment, a semiconductor package includes a first conductive member, a second conductive member, a plurality of semiconductor devices, a wiring member, a first connection member, and a second connection member. The plurality of semiconductor devices is provided between the first conductive member and the second conductive member. One of the semiconductor devices includes a semiconductor member, a first electrode, a first control electrode, a second control electrode, and a second electrode. The first and second conductive members are electrically connected to the first and second electrodes, respectively. The wiring member includes first, second and third wiring layers, and an insulating region. A part of the insulating region is located between the first wiring layer and the third wiring layer, and between the third wiring layer and the second wiring layer. The second wiring layer includes a first connection region and a second connection region.
    Type: Application
    Filed: February 14, 2023
    Publication date: February 15, 2024
    Inventors: Satoshi YOSHIDA, Tatsunori SAKANO, Ryohei GEJO
  • Patent number: 11837654
    Abstract: A semiconductor device includes first and second electrodes, a semiconductor part therebetween, and a control electrode between the semiconductor part and the first electrode. The semiconductor part includes first, third and fifth layers of a first conductivity type and second and fourth layers of a second conductivity type. The second layer is provided between the first layer and the first electrode. The third layer is provided between the second layer and the first electrode. The fourth layer and the fifth layer are selectively provided between the first layer and the second electrode. In a method for controlling the semiconductor device, first to third voltages are applied in order to the control electrode while a p-n junction between the first and second layers is biased in a forward direction. The second and third voltages are greater than the first voltage, and the third voltage is less than the second voltage.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: December 5, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Ryohei Gejo, Tatsunori Sakano
  • Patent number: 11824056
    Abstract: A semiconductor device includes a semiconductor part, first and second electrodes, a control electrode and a control interconnect. The semiconductor part includes first to sixth layers and is provided between the first and second electrodes. The second layer is provided between the first layer and the second electrode. The third layer is provided between the second layer and the second electrode. The fourth and fifth layers are arranged between the first layer and the first electrode. The second electrode and the control interconnect are arranged on the semiconductor part. The control electrode is provided between the second electrode and the semiconductor part. The sixth layer is provided between the first layer and the control interconnect. The fifth semiconductor layer is provided between the first electrode and the sixth layer. The first semiconductor layer includes a carrier trap provided between the fifth and sixth layers.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: November 21, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Ryohei Gejo, Akiyo Minamikawa, Shigeaki Hayase
  • Patent number: 11784246
    Abstract: According to one embodiment, a semiconductor device includes first to fourth electrodes, a semiconductor member, and first and second insulating members. The semiconductor member is located between the second and first electrodes, and includes a first semiconductor region a second semiconductor region between the first semiconductor region and the first electrode, a third semiconductor region between the second semiconductor region and the first electrode, a fourth semiconductor region between the second semiconductor region and the first electrode, a fifth semiconductor region between the first semiconductor region and the second electrode, a sixth semiconductor region between the fifth semiconductor region and the second electrode, and a seventh semiconductor region between the fifth semiconductor region and the second electrode. A portion of the first insulating member is between the third electrode and the semiconductor member.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: October 10, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Ryohei Gejo, Tatsunori Sakano, Takahiro Kato
  • Patent number: 11777028
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a first conductive member, a semiconductor member, and a first insulating member. The third electrode includes a third electrode end portion and a third electrode other-end portion. The first conductive member includes a first conductive member end portion and a first conductive member other-end portion. The first conductive member is electrically connected with one of the second electrode or the third electrode. The semiconductor member includes first to fourth semiconductor regions. The first semiconductor region includes first and second partial regions. The third semiconductor region is electrically connected with the second electrode. The fourth semiconductor region is electrically connected with the first electrode. At least a portion of the first insulating member is between the semiconductor member and the third electrode and between the semiconductor member and the first conductive member.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: October 3, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yusuke Kobayashi, Akihiro Goryu, Ryohei Gejo, Hiro Gangi, Tomoaki Inokuchi, Shotaro Baba, Tatsuya Nishiwaki, Tsuyoshi Kachi
  • Patent number: 11777025
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, first and second electrodes, a gate electrode, a gate terminal, a first conductive member, a first terminal, and a first insulating member. The semiconductor member includes first and second semiconductor regions, and a third semiconductor region provided between the first and second semiconductor regions. The first electrode is electrically connected to the first semiconductor region. The second electrode is electrically connected to the second semiconductor region. The gate terminal is electrically connected to the gate electrode. The first conductive member is electrically insulated from the first and second electrodes, and the gate electrode. The first terminal is electrically connected to the first conductive member.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: October 3, 2023
    Assignees: KABUSHIKA KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yusuke Kobayashi, Tatsunori Sakano, Hiro Gangi, Tomoaki Inokuchi, Takahiro Kato, Yusuke Hayashi, Ryohei Gejo, Tatsuya Nishiwaki
  • Publication number: 20230307444
    Abstract: A semiconductor device according to the embodiment includes: a transistor region including a first trench, a first gate electrode provided in the first trench, a second trench, a second gate electrode provided in the second trench, a third trench, and a third gate electrode provided in the third trench; a diode region including a fifth trench and a conductive layer provided in the fifth trench; a boundary region including a fourth trench and a fourth gate electrode provided in the fourth trench, the boundary region being provided between the transistor region and the diode region; a first electrode pad electrically connected to the first gate electrode; a second electrode pad electrically connected to the second gate electrode; and a third electrode pad electrically connected to the third gate electrode and the fourth gate electrode.
    Type: Application
    Filed: September 9, 2022
    Publication date: September 28, 2023
    Inventors: Tomoko MATSUDAI, Yoko IWAKAJI, Ryohei GEJO
  • Publication number: 20230299178
    Abstract: A semiconductor device includes a first electrode, a plurality of unit element regions, and a partitioning region. Each of the unit element regions includes a first semiconductor part, a second electrode, and a first conductive part. The first semiconductor part includes first to third semiconductor regions. The first semiconductor region is located above the first electrode. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on the second semiconductor region. The second electrode is located on the second and third semiconductor regions. The first conductive part faces the second semiconductor region via a first insulating film. At least a portion of the plurality of unit element regions includes a common pattern. The partitioning region includes a second semiconductor part and partitions the plurality of unit element regions. The second semiconductor part is continuous with the first semiconductor part.
    Type: Application
    Filed: August 31, 2022
    Publication date: September 21, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tatsuya NISHIWAKI, Ryohei GEJO, Tomoko MATSUDAI
  • Publication number: 20230268428
    Abstract: S1?S2<S3 being satisfied, where S1 is a surface area of the first gate electrode and the third semiconductor layer facing each other via the first insulating film, S2 is a surface area of the second gate electrode and the third semiconductor layer facing each other via the second insulating film, and S3 is a surface area of the third gate electrode and the third semiconductor layer facing each other via the third insulating film.
    Type: Application
    Filed: July 1, 2022
    Publication date: August 24, 2023
    Inventors: Ryohei GEJO, Tomoko MATSUDAI, Yoko IWAKAJI
  • Publication number: 20230253485
    Abstract: According to one embodiment, a semiconductor device includes first to fourth electrodes, a semiconductor member, and an insulating member. The semiconductor member includes first to sixth semiconductor regions. The third semiconductor region includes first and second partial regions. A part of the fourth semiconductor region is between the second partial and second semiconductor regions. The fifth semiconductor region is between the second partial region and a part of the fourth semiconductor region. The sixth semiconductor region is between the first electrode and the first semiconductor region. The second electrode is electrically connected to the second semiconductor region. The fourth electrode is between the first partial region and the third electrode. A part of the insulating member is provided between the semiconductor member and the third electrode, between the semiconductor member and the fourth electrode, and between the third and fourth electrodes.
    Type: Application
    Filed: August 2, 2022
    Publication date: August 10, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Takahiro KATO, Tatsunori SAKANO, Yusuke KOBAYASHI, Ryohei GEJO
  • Publication number: 20230238944
    Abstract: According to one embodiment, a drive device includes a drive circuit configured to drive a semiconductor device. The semiconductor device includes first to fourth electrodes, a semiconductor member, and an insulating member. The semiconductor member includes first to fourth semiconductor region. The first semiconductor region includes first to third partial regions. The first semiconductor region is between the first electrode and the second semiconductor region. The third semiconductor region is between the first and second semiconductor regions. The fourth semiconductor region is between the first electrode and the first semiconductor region. The second electrode is electrically connected to the second semiconductor region. The first partial region is between the fourth semiconductor region and the third electrode. The second partial region is between the fourth semiconductor region and the fourth electrode.
    Type: Application
    Filed: July 12, 2022
    Publication date: July 27, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tatsunori SAKANO, Ryohei GEJO, Tomoko MATSUDAI
  • Publication number: 20230223464
    Abstract: A semiconductor device includes a semiconductor part, first and second electrodes and a control electrode. The semiconductor part is provided between the first and second electrodes. The control electrode is provided between the semiconductor part and the second electrode. The semiconductor part includes first, third and fifth layers of a first conductivity type, and second, fourth, sixth and seventh layers of a second conductivity type. The second layer is provided between the first layer and the second electrode. The third layer is provided between the second layer and the second electrode. The fourth and fifth layers are provided between the first layer and the first electrode. The sixth layer surrounds the second and third layers. The seventh layer is provided between the first layer and the first electrode. The seventh layer surrounds the fourth and fifth layers and is apart from the fourth and fifth layers.
    Type: Application
    Filed: July 19, 2022
    Publication date: July 13, 2023
    Inventor: Ryohei GEJO
  • Publication number: 20230123438
    Abstract: A semiconductor device includes first and second electrodes, a semiconductor part therebetween, and a control electrode between the semiconductor part and the first electrode. The semiconductor part includes first, third and fifth layers of a first conductivity type and second and fourth layers of a second conductivity type. The second layer is provided between the first layer and the first electrode. The third layer is provided between the second layer and the first electrode. The fourth layer and the fifth layer are selectively provided between the first layer and the second electrode. In a method for controlling the semiconductor device, first to third voltages are applied in order to the control electrode while a p-n junction between the first and second layers is biased in a forward direction. The second and third voltages are greater than the first voltage, and the third voltage is less than the second voltage.
    Type: Application
    Filed: December 20, 2022
    Publication date: April 20, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Ryohei GEJO, Tatsunori SAKANO
  • Publication number: 20230031686
    Abstract: A semiconductor device according to an embodiment includes a first trench, a first gate electrode in the first trench, a second trench, a second gate electrode provided in the second trench, a third trench, a third gate electrode in the third trench, a first electrode pad electrically connected to the first gate electrode, a second electrode pad electrically connected to the second gate electrode, and a third electrode pad electrically connected to the third gate electrode, in which a thickness of a conductive semiconductor region opposed to the third gate electrode is smaller than a thickness of a conductive semiconductor region opposed to the first gate electrode, and in which the thickness of the conductive semiconductor region opposed to the third gate electrode is smaller than a thickness of a conductive type semiconductor region opposed to the second gate electrode.
    Type: Application
    Filed: September 6, 2022
    Publication date: February 2, 2023
    Inventors: Yoko IWAKAJI, Tomoko MATSUDAI, Ryohei GEJO
  • Patent number: 11563112
    Abstract: A semiconductor device includes first and second electrodes, a semiconductor part therebetween, and a control electrode between the semiconductor part and the first electrode. The semiconductor part includes first, third and fifth layers of a first conductivity type and second and fourth layers of a second conductivity type. The second layer is provided between the first layer and the first electrode. The third layer is provided between the second layer and the first electrode. The fourth layer and the fifth layer are selectively provided between the first layer and the second electrode. In a method for controlling the semiconductor device, first to third voltages are applied in order to the control electrode while a p-n junction between the first and second layers is biased in a forward direction. The second and third voltages are greater than the first voltage, and the third voltage is less than the second voltage.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: January 24, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Ryohei Gejo, Tatsunori Sakano
  • Publication number: 20230006057
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a first wiring member, a semiconductor member, and an insulating member. The first wiring member includes a first extending portion. A part of the third electrode is between the first electrode and the first extending portion. An other part of the third electrode is between the first and second electrodes. The semiconductor member is provided between the first and second electrodes and between the first electrode and the first extending portion. The semiconductor member includes first to sixth semiconductor regions. The first semiconductor region includes first and second partial regions. The first partial region is located between the first electrode and the third electrode. The insulating member includes the first insulating region. The first insulating region is provided between the third electrode and the semiconductor member.
    Type: Application
    Filed: February 3, 2022
    Publication date: January 5, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Ryohei GEJO, Tatsunori SAKANO