Patents by Inventor Ryohei GEJO
Ryohei GEJO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10700184Abstract: According to one embodiment, a semiconductor device a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a fifth semiconductor region, a sixth semiconductor region, a seventh semiconductor region, an eighth semiconductor region, a gate electrode, a ninth semiconductor region, and a second electrode. The first, second, and fourth semiconductor regions are provided on the first electrode. The third semiconductor region is provided between the first and second semiconductor regions. The fifth semiconductor region is provided on the first, second, third, and fourth semiconductor regions. The sixth and seventh semiconductor regions are provided on the fifth semiconductor region. The eighth semiconductor region is provided on a portion of the seventh semiconductor region. The ninth semiconductor region is provided around the sixth semiconductor region and the seventh semiconductor region.Type: GrantFiled: September 4, 2018Date of Patent: June 30, 2020Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Tomohiro Tamaki, Kazutoshi Nakamura, Ryohei Gejo
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Patent number: 10636898Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer selectively provided on the first semiconductor layer, a third semiconductor layer selectively provided on the second semiconductor layer, and a control electrode facing a portion of the second semiconductor layer via a first insulating film. The device further includes a fourth semiconductor layer provided on a lower surface side of the first semiconductor layer, a fifth semiconductor layer arranged with the fourth semiconductor layer along a lower surface of the first semiconductor layer, and a sixth semiconductor layer provided between the first and fifth semiconductor layers. The sixth semiconductor layer is connected to the fourth semiconductor layer. The device includes a connecting portion positioned between the first and fifth semiconductor layers.Type: GrantFiled: November 29, 2018Date of Patent: April 28, 2020Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventor: Ryohei Gejo
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Publication number: 20200058779Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer selectively provided on the first semiconductor layer, a third semiconductor layer selectively provided on the second semiconductor layer, and a control electrode facing a portion of the second semiconductor layer via a first insulating film. The device further includes a fourth semiconductor layer provided on a lower surface side of the first semiconductor layer, a fifth semiconductor layer arranged with the fourth semiconductor layer along a lower surface of the first semiconductor layer, and a sixth semiconductor layer provided between the first and fifth semiconductor layers. The sixth semiconductor layer is connected to the fourth semiconductor layer. The device includes a connecting portion positioned between the first and fifth semiconductor layers.Type: ApplicationFiled: November 29, 2018Publication date: February 20, 2020Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventor: Ryohei GEJO
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Publication number: 20190296132Abstract: According to one embodiment, a semiconductor device a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a fifth semiconductor region, a sixth semiconductor region, a seventh semiconductor region, an eighth semiconductor region, a gate electrode, a ninth semiconductor region, and a second electrode. The first, second, and fourth semiconductor regions are provided on the first electrode. The third semiconductor region is provided between the first and second semiconductor regions. The fifth semiconductor region is provided on the first, second, third, and fourth semiconductor regions. The sixth and seventh semiconductor regions are provided on the fifth semiconductor region. The eighth semiconductor region is provided on a portion of the seventh semiconductor region. The ninth semiconductor region is provided around the sixth semiconductor region and the seventh semiconductor region.Type: ApplicationFiled: September 4, 2018Publication date: September 26, 2019Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Tomohiro TAMAKI, Kazutoshi NAKAMURA, Ryohei GEJO
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Patent number: 10418470Abstract: A semiconductor device according to an embodiment includes a first diode portion including a first trench extending in a first direction, and a first trench electrode; a second diode portion adjacent to the first diode portion in the first direction and includes a second trench extending in the first direction, and a second trench electrode and of which the width in the first direction is greater than the width of the first diode portion in a second direction perpendicular to the first direction; and a first IGBT portion adjacent to the first diode portion in the second direction and is adjacent to the second diode portion in the first direction and includes a third trench extending in the first direction, and a first gate electrode.Type: GrantFiled: March 6, 2018Date of Patent: September 17, 2019Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Ryohei Gejo, Kazutoshi Nakamura, Norio Yasuhara, Tomohiro Tamaki
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Publication number: 20190259747Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a gate electrode, a fifth semiconductor region, a sixth semiconductor region, a seventh semiconductor region, an eighth semiconductor region, and a second electrode. The first semiconductor region is provided on the first electrode. The eighth semiconductor region surrounds the third semiconductor region, the sixth semiconductor region, and the seventh semiconductor region. The eighth semiconductor region includes a first region and a second region respectively arranged with the third semiconductor region and the seventh semiconductor region in a third direction. A lower end of the second region is positioned higher than a lower end of the first region.Type: ApplicationFiled: July 9, 2018Publication date: August 22, 2019Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventor: Ryohei GEJO
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Patent number: 10297593Abstract: According to one embodiment, a semiconductor device includes a first region having an insulated gate bipolar transistor and a second region having a diode. The first region and the second region are formed in a same chip. A breakdown voltage of the second region is lower than a breakdown voltage of the first region.Type: GrantFiled: January 26, 2016Date of Patent: May 21, 2019Assignee: Kabushiki Kaisha ToshibaInventor: Ryohei Gejo
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Publication number: 20190081162Abstract: A semiconductor device according to an embodiment includes a first diode portion including a first trench extending in a first direction, and a first trench electrode; a second diode portion adjacent to the first diode portion in the first direction and includes a second trench extending in the first direction, and a second trench electrode and of which the width in the first direction is greater than the width of the first diode portion in a second direction perpendicular to the first direction; and a first IGBT portion adjacent to the first diode portion in the second direction and is adjacent to the second diode portion in the first direction and includes a third trench extending in the first direction, and a first gate electrode.Type: ApplicationFiled: March 6, 2018Publication date: March 14, 2019Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Ryohei GEJO, Kazutoshi NAKAMURA, Norio YASUHARA, Tomohiro TAMAKI
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Patent number: 10083957Abstract: According to one embodiment, a semiconductor device includes a first electrode, first regions, second regions, an eighth semiconductor region, a ninth semiconductor region of the second conductivity type, a tenth semiconductor region, second electrodes, and a third electrode. Each first region includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, and a gate electrode. The first regions and the second regions alternate in the second direction. Each of the second regions includes a fifth semiconductor region, a sixth semiconductor region, and a seventh semiconductor region. The eighth semiconductor region is provided between the first semiconductor regions and between the fifth semiconductor regions. The eighth semiconductor region is electrically connected to the first semiconductor regions. The third electrode is provided on the tenth semiconductor region with a first insulating layer interposed.Type: GrantFiled: September 8, 2017Date of Patent: September 25, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Tomohiro Tamaki, Kazutoshi Nakamura, Ryohei Gejo
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Publication number: 20180226399Abstract: According to one embodiment, a semiconductor device includes a first electrode, first regions, second regions, an eighth semiconductor region, a ninth semiconductor region of the second conductivity type, a tenth semiconductor region, second electrodes, and a third electrode. Each first region includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, and a gate electrode. The first regions and the second regions alternate in the second direction. Each of the second regions includes a fifth semiconductor region, a sixth semiconductor region, and a seventh semiconductor region. The eighth semiconductor region is provided between the first semiconductor regions and between the fifth semiconductor regions. The eighth semiconductor region is electrically connected to the first semiconductor regions. The third electrode is provided on the tenth semiconductor region with a first insulating layer interposed.Type: ApplicationFiled: September 8, 2017Publication date: August 9, 2018Inventors: Tomohiro Tamaki, Kazutoshi Nakamura, Ryohei Gejo
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Patent number: 9761582Abstract: A semiconductor device comprising: a first electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; a third semiconductor region of the second conductivity type provided between the first semiconductor region and the second semiconductor region on the first electrode and having a higher carrier concentration of the second conductivity type than the second semiconductor region; a fourth semiconductor region; a fifth semiconductor region; a sixth semiconductor region; a seventh semiconductor region; a gate electrode; a gate insulating layer; and a second electrode provided on the fifth semiconductor region and the seventh semiconductor region.Type: GrantFiled: September 2, 2016Date of Patent: September 12, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Ryohei Gejo, Kazutoshi Nakamura, Norio Yasuhara, Tomohiro Tamaki
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Publication number: 20170110449Abstract: A semiconductor device comprising: a first electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; a third semiconductor region of the second conductivity type provided between the first semiconductor region and the second semiconductor region on the first electrode and having a higher carrier concentration of the second conductivity type than the second semiconductor region; a fourth semiconductor region; a fifth semiconductor region; a sixth semiconductor region; a seventh semiconductor region; a gate electrode; a gate insulating layer; and a second electrode provided on the fifth semiconductor region and the seventh semiconductor region.Type: ApplicationFiled: September 2, 2016Publication date: April 20, 2017Inventors: Ryohei Gejo, Kazutoshi Nakamura, Norio Yasuhara, Tomohiro Tamaki
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Publication number: 20160218101Abstract: According to one embodiment, a semiconductor device includes a first region having an insulated gate bipolar transistor and a second region having a diode. The first region and the second region are formed in a same chip. A breakdown voltage of the second region is lower than a breakdown voltage of the first region.Type: ApplicationFiled: January 26, 2016Publication date: July 28, 2016Inventor: Ryohei Gejo
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Patent number: 9324815Abstract: According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode and being in contact with the first electrode; a second semiconductor layer including a first part and a second part, and the second part being contact with the first electrode, and the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer; a third semiconductor layer provided between the second semiconductor layer and the second electrode, and having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer; and a fourth semiconductor layer provided between the third semiconductor layer and the second electrode, and being in contact with the second electrode.Type: GrantFiled: May 1, 2015Date of Patent: April 26, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tsuneo Ogura, Tomoko Matsudai, Yuuichi Oshino, Yoshiko Ikeda, Kazutoshi Nakamura, Ryohei Gejo
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Patent number: 9159722Abstract: A semiconductor device includes a transistor region and diode region. A plurality of transistors is in the transistor region and at least one diode is in the diode region. The transistors include first and second body regions of a first conductivity type. The dopant concentration in the second body region is greater than the dopant concentration in the first body region. The diode includes first and second anode regions of the first conductivity type. The dopant concentration in the second anode region is greater than the dopant concentration in the first anode region. A total dopant amount in the second body region within a first block portion of the semiconductor substrate is greater than a total dopant amount in the second anode layer within a second block portion of the semiconductor substrate of the same size as the first block portion.Type: GrantFiled: July 24, 2014Date of Patent: October 13, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Shinichiro Misu, Ryohei Gejo, Norio Yasuhara
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Publication number: 20150263150Abstract: According to one embodiment, a semiconductor device including: a first electrode; a second electrode having a portion extending toward the first electrode side; a first semiconductor layer; a first semiconductor region provided between the first semiconductor layer and the second electrode; a second semiconductor region provided between the first semiconductor region and the second electrode, and the second semiconductor region being in contact with the portion; a third electrode provided between the first electrode and the portion, and the third electrode being connected to the portion; a fourth electrode provided on the first semiconductor layer, the first semiconductor region, and the second semiconductor region via a second insulating film; and a third semiconductor region provided between the first semiconductor region and the second semiconductor region, and the third semiconductor region having a higher impurity concentration than the first semiconductor region.Type: ApplicationFiled: September 10, 2014Publication date: September 17, 2015Inventors: Tomoko Matsudai, Tsuneo Ogura, Kazutoshi Nakamura, Ryohei Gejo
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Publication number: 20150255629Abstract: A semiconductor device includes: a first semiconductor layer of a first conductive type having a first side and an opposed second side; a second semiconductor layer of a second conductive type formed on the first side; a third semiconductor layer of a second conductive type partially formed in the second semiconductor layer; a fourth semiconductor layer of a first conductive type formed between the first semiconductor layer and the second semiconductor layer, the fourth semiconductor layer facing the third semiconductor layer, the fourth semiconductor layer including a first region which has a first dopant concentration and a second region which has a second dopant concentration higher than the first dopant concentration; a fifth semiconductor layer of a first conductive type formed on the second side; and a conductor contacting the first semiconductor layer, the second semiconductor layer and the third semiconductor layer via an insulation film.Type: ApplicationFiled: September 2, 2014Publication date: September 10, 2015Inventors: Ryohei GEJO, Bungo TANAKA
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Publication number: 20150236104Abstract: According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode and being in contact with the first electrode; a second semiconductor layer including a first part and a second part, and the second part being contact with the first electrode, and the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer; a third semiconductor layer provided between the second semiconductor layer and the second electrode, and having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer; and a fourth semiconductor layer provided between the third semiconductor layer and the second electrode, and being in contact with the second electrode.Type: ApplicationFiled: May 1, 2015Publication date: August 20, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsuneo OGURA, Tomoko MATSUDAI, Yuuichi OSHINO, Yoshiko IKEDA, Kazutoshi NAKAMURA, Ryohei GEJO
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Patent number: 9054066Abstract: According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode and being in contact with the first electrode; a second semiconductor layer including a first part and a second part, and the second part being contact with the first electrode, and the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer; a third semiconductor layer provided between the second semiconductor layer and the second electrode, and having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer; and a fourth semiconductor layer provided between the third semiconductor layer and the second electrode, and being in contact with the second electrode.Type: GrantFiled: August 29, 2013Date of Patent: June 9, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tsuneo Ogura, Tomoko Matsudai, Yuuichi Oshino, Yoshiko Ikeda, Kazutoshi Nakamura, Ryohei Gejo
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Publication number: 20150155277Abstract: A semiconductor device includes a transistor region and diode region. A plurality of transistors is in the transistor region and at least one diode is in the diode region. The transistors include first and second body regions of a first conductivity type. The dopant concentration in the second body region is greater than the dopant concentration in the first body region. The diode includes first and second anode regions of the first conductivity type. The dopant concentration in the second anode region is greater than the dopant concentration in the first anode region. A total dopant amount in the second body region within a first block portion of the semiconductor substrate is greater than a total dopant amount in the second anode layer within a second block portion of the semiconductor substrate of the same size as the first block portion.Type: ApplicationFiled: July 24, 2014Publication date: June 4, 2015Inventors: Tsuneo OGURA, Shinichiro MISU, Ryohei GEJO, Norio YASUHARA