Patents by Inventor Ryohei Miyagawa
Ryohei Miyagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140117486Abstract: A solid-state imaging apparatus having a plurality of pixels, comprising: a substrate; a wiring layer formed on the substrate and including an insulating film and a plurality of wires; a plurality of lower electrodes formed on the wiring layer in one-to-one correspondence with the plurality of pixels; a photoelectric conversion film formed covering the plurality of lower electrodes; a light-transmissive upper electrode formed on the photoelectric conversion film; and a shield electrode extending through a gap between each pair of adjacent lower electrodes among the plurality of lower electrodes, the shield electrode having a fixed potential and being electrically insulated from the plurality of lower electrodes.Type: ApplicationFiled: December 27, 2013Publication date: May 1, 2014Applicant: PANASONIC CORPORATIONInventors: Hiroyuki DOI, Mitsuo YASUHIRA, Ryohei MIYAGAWA, Yoshiyuki OHMORI
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Publication number: 20140103400Abstract: A solid-state imaging device includes: a first electrode formed above a semiconductor substrate; a photoelectric conversion film formed on the first electrode and for converting light into signal charges; a second electrode formed on the photoelectric conversion film; a charge accumulation region electrically connected to the first electrode and for accumulating the signal charges converted from the light by the photoelectric conversion film; a reset gate electrode for resetting the charge accumulation region; an amplification transistor for amplifying the signal charges accumulated in the charge accumulation region; and a contact plug in direct contact with the charge accumulation region, comprising a semiconductor material, and for electrically connecting to each other the first electrode and the charge accumulation region.Type: ApplicationFiled: December 18, 2013Publication date: April 17, 2014Applicant: Panasonic CorporationInventors: Yusuke SAKATA, Mitsuyoshi MORI, Yutaka HIROSE, Hiroshi MASUDA, Hitoshi KURIYAMA, Ryohei MIYAGAWA
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Publication number: 20140091368Abstract: A solid-state imaging device including: a semiconductor substrate of a first conductivity type, having a fixed electric potential; a dark-current drain region of a second conductivity type, formed on a portion of the semiconductor substrate; a connection region of the first conductivity type, formed on another portion of the semiconductor substrate where the dark-current drain region is not formed; a well region of the first conductivity type, covering the dark-current drain region and the connection region; and a first region and a second region, formed within the well region and constituting a part of a read transistor that reads signal charge generated by photoelectric conversion. The well region is maintained at a fixed electric potential by being connected to the semiconductor substrate via the connection region.Type: ApplicationFiled: December 5, 2013Publication date: April 3, 2014Applicant: PANASONIC CORPORATIONInventor: Ryohei MIYAGAWA
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Publication number: 20130341491Abstract: A solid-state imaging device includes: a substrate; a plurality of first electrodes arranged in a matrix above the substrate, and electrically isolated from each other; an insulator layer covering the first electrodes, having a planarized upper surface, and comprising an insulator; a photoelectric conversion film which is formed above the insulator layer, and converts light into signal charges; a second electrode formed above the photoelectric conversion film; and a signal readout circuit which is formed on the substrate, and generates a readout signal by detecting an amount of current change or voltage change caused by the signal charges at each of the first electrodes, in which the insulator layer allows conduction of at least electrons or holes by quantum mechanical tunneling.Type: ApplicationFiled: August 27, 2013Publication date: December 26, 2013Applicant: Panasonic CorporationInventors: Yutaka HIROSE, Ryohei MIYAGAWA, Tetsuya UEDA, Yoshihisa KATO
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Patent number: 8009217Abstract: In a solid-state imaging device, provided is a solid-state imaging device in which a first gate insulation film 22 for the readout transistor 12 in a pixel is formed so as to be thicker than a second gate insulation film 23 for an amplification transistor 14 in the pixel, and the second gate insulation film 23 for the amplification transistor 14 in the pixel is formed so as to be thicker than a third gate insulation film 24 for an n-type micro transistor 17 and a p-type micro transistor 18 in a peripheral region outside the pixel, whereby it is possible to suppress a 1/f noise of the amplification transistor 14 and also possible to increase a saturated charge amount.Type: GrantFiled: April 22, 2009Date of Patent: August 30, 2011Assignee: Panasonic CorporationInventor: Ryohei Miyagawa
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Patent number: 7936036Abstract: A solid-state image sensor includes: a trench isolation region; a photodiode region for converting incident light to signal charges and accumulating the signal charges therein; a floating diffusion region for accumulating the signal charges of the photodiode region; a gate electrode formed over the element formation region located between the photodiode region and the floating diffusion region, and formed so that both ends of the gate electrode respectively overlap a part of the photodiode region and a part of the floating diffusion region; and an inactive layer formed in a region located in a bottom portion and sidewall portions of the trench isolation region. An impurity concentration in a region located under the gate electrode in the inactive layer is lower than that in a region other than the region located under the gate electrode in the inactive layer.Type: GrantFiled: May 1, 2009Date of Patent: May 3, 2011Assignee: Panasonic CorporationInventors: Shouzi Tanaka, Ryohei Miyagawa
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Publication number: 20110080508Abstract: In a solid-state image pickup device, it is difficult to match an optimum incidence angle corresponding to an image height of a pixel array region with light incidence characteristics of a camera lens, thereby causing image quality deterioration due to sensitivity shading. Respective microlenses are disposed in a two-dimensional manner, i.e., in a row and a column directions. In particular, the microlenses are disposed such that each side of a disposition region where the microlenses are disposed has a concave curve with respect to a line connecting adjacent vertexes of the disposition region. In other words, a distance AH (AV) between center points of a pair of facing sides of the disposition region is set to be smaller than a distance BH (BV) between neighboring vertexes of the disposition region.Type: ApplicationFiled: November 17, 2010Publication date: April 7, 2011Applicant: PANASONIC CORPORATIONInventors: Motonari KATSUNO, Ryohei MIYAGAWA
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Patent number: 7906827Abstract: A solid-state imaging device includes a first wiring layer, a second wiring layer, a substrate contact, and a first contact. The arrangement of the substrate contact with respect to a light-receiving section forming a peripheral pixel is shifted, or not shifted, from the arrangement of the substrate contact with respect to a light-receiving section forming a central pixel, by a shift amount r from the peripheral portion toward the central portion. The arrangement of the first contact with respect to the light-receiving section of the peripheral pixel is shifted from the arrangement of the first contact with respect to the light-receiving section of the central pixel, by a shift amount s1 from the peripheral portion toward the central portion. The shift amount s1 is greater than the shift amount r.Type: GrantFiled: July 14, 2008Date of Patent: March 15, 2011Assignee: Panasonic CorporationInventors: Motonari Katsuno, Ryohei Miyagawa, Hirohisa Ohtsuki
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Publication number: 20110006387Abstract: A photodiode is formed for each pixel of a semiconductor substrate. An insulating film is formed on the semiconductor substrate, the insulating film having a depressed portion over the photodiode. A buried film having a higher refractive index than the insulating film is formed in the depressed portion. The cross sectional area of the depressed portion along a plane parallel to the light-receiving surface of the semiconductor substrate gradually increases at positions further away from the light-receiving surface of the semiconductor substrate.Type: ApplicationFiled: June 24, 2010Publication date: January 13, 2011Inventors: Motonari KATSUNO, Ryohei MIYAGAWA
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Patent number: 7863661Abstract: Provided is a solid-state imaging device including unit pixels, wherein the unit pixels include two kinds of unit pixels including a first unit pixel and a second unit pixel that are formed on a common well on a semiconductor substrate. The first unit pixel includes: at least one photoelectric conversion region which converts light into a signal charge; the first semiconductor region that is formed on the common well and has a conductivity type identical to that of the common well; and the first contact electrically connected to the first semiconductor region. The second unit pixel includes: at least one photoelectric conversion region; the second semiconductor region that is formed on the common well and has a conductivity type opposite to that of the common well; and the second contact electrically connected to the second semiconductor region.Type: GrantFiled: March 24, 2008Date of Patent: January 4, 2011Assignee: Panasonic CorporationInventors: Motonari Katsuno, Ryohei Miyagawa, Hirohisa Ohtsuki
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Patent number: 7859587Abstract: In a solid-state image pickup device, it is difficult to match an optimum incidence angle corresponding to an image height of a pixel array region with light incidence characteristics of a camera lens, thereby causing image quality deterioration due to sensitivity shading. Respective microlenses are disposed in a two-dimensional manner, i.e., in a row and a column directions. In particular, the microlenses are disposed such that each side of a disposition region where the microlenses are disposed has a concave curve with respect to a line connecting adjacent vertexes of the disposition region. In other words, a distance AH (AV) between center points of a pair of facing sides of the disposition region is set to be smaller than a distance BH (BV) between neighboring vertexes of the disposition region.Type: GrantFiled: March 20, 2007Date of Patent: December 28, 2010Assignee: Panasonic CorporationInventors: Motonari Katsuno, Ryohei Miyagawa
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Patent number: 7847848Abstract: In a MOS-type solid-state imaging device 1, in pixels 101 to 104 in which lines in an upper layer (charge transfer lines 1018 to 1048) are formed in shifted positions located toward a center L1 of an image area, each two oppositely disposed pixels with the center L1 of the image area sandwiched therebetween, such as a pixel 101 and a pixel 104 have the following relation. In each of the pixels 101 and 104, power supply lines 1016 and 1046, vertical signal lines 1017 and 1047, and charge transfer lines 1018 and 1048 relating to each of the pixels 101 and 104 are arranged symmetrically with respect to an imaginary plane extending from the center L1 of a sensor 10 in a direction orthogonal to the drawing page in an X-axis direction.Type: GrantFiled: January 4, 2008Date of Patent: December 7, 2010Assignee: Panasonic CorporationInventors: Hirohisa Ohtsuki, Ryohei Miyagawa, Motonari Katsuno, Mikiya Uchida
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Publication number: 20100270637Abstract: A solid-state imaging device includes: an imaging area in which light receiving portions are disposed; an interconnect layer disposed on the light receiving portions, the interconnect layer including metal interconnects having openings and first insulating films; inner-layer lenses formed over the interconnect layer in one-to-one relationship with the light receiving portions; a transparent second insulating film formed on the interconnect layer and the inner-layer lenses; top lenses formed on the second insulating film in one-to-one relationship with the light receiving portions, an upper face of each of the top lenses being a convexly curved face; and a transparent film on the top lenses, the transparent film being formed of a material having a refractive index smaller than a refractive index of the top lenses. In this way, a focal point of at least part of incident light can be situated above a semiconductor substrate.Type: ApplicationFiled: July 12, 2010Publication date: October 28, 2010Applicant: Panasonic CorporationInventors: Motonari KATSUNO, Ryohei MIYAGAWA
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Patent number: 7800191Abstract: A pixel array is provided in which cells are arranged in a matrix. Each cell includes a photodiode, an FD, a transfer transistor, a reset transistor, an amplifying transistor having a gate electrode connected to the FD, a drain connected to a power supply line, and a source connected to a vertical signal line, and an FD wire. The FD wire is provided in a first wiring line, and the vertical signal line is provided in a second wiring line positioned over the first wiring layer. Since the potential of the FD wire follows the potential of the vertical signal line, it is possible to suppress a variation in capacitance occurring in the FD when a position of the vertical signal is shifted, depending on a position of the cell.Type: GrantFiled: March 12, 2007Date of Patent: September 21, 2010Assignee: Panasonic CorporationInventors: Hirohisa Ohtsuki, Motonari Katsuno, Ryohei Miyagawa
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Patent number: 7777260Abstract: A solid-state imaging device includes: an imaging area in which light receiving portions are disposed; an interconnect layer disposed on the light receiving portions, the interconnect layer including metal interconnects having openings and first insulating films; inner-layer lenses formed over the interconnect layer in one-to-one relationship with the light receiving portions; a transparent second insulating film formed on the interconnect layer and the inner-layer lenses; top lenses formed on the second insulating film in one-to-one relationship with the light receiving portions, an upper face of each of the top lenses being a convexly curved face; and a transparent film on the top lenses, the transparent film being formed of a material having a refractive index smaller than a refractive index of the top lenses. In this way, a focal point of at least part of incident light can be situated above a semiconductor substrate.Type: GrantFiled: July 2, 2008Date of Patent: August 17, 2010Assignee: Panasonic CorporationInventors: Motonari Katsuno, Ryohei Miyagawa
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Publication number: 20100187582Abstract: A solid-state imaging device having a plurality of image pixels arranged along a main surface of a semiconductor substrate, wherein each of the plurality of image pixels includes a photodiode that converts incident light into an electric charge and a transmission gate that is formed so as to have a crossing area that partially passes over the photodiode when seen from the thickness direction of the semiconductor substrate. The transmission gate of the solid-state imaging device is formed in a manner that (i) a first region including a laminated body of a silicon film and a silicide film, and (ii) a second region that includes the silicon film and does not include the silicide film, both arranged along a main surface of the semiconductor substrate, and the second region in the transmission gate is formed in at least one part of the crossing area.Type: ApplicationFiled: April 1, 2010Publication date: July 29, 2010Applicant: PANASONIC CORPORATIONInventors: Motonari Katsuno, Ryohei Miyagawa
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Patent number: 7755150Abstract: An N-type epitaxial layer 115, which is formed above an N-type semiconductor substrate 114 in each of a pixel region and a peripheral circuit region; a first P-type well 1 formed above the N-type epitaxial layer 115 in the pixel region; and light receiving regions 117, which are formed within the first P-type well 1 and each of which is a component of a photodiode, are included. The peripheral circuit region includes: second P-type wells 2, which are formed from a surface 200 of the peripheral circuit region to a desired depth and each of which is a component of an N-Channel MOS transistor; an N-type well 3 which is formed from the surface 200 of the peripheral circuit region to a desired depth and which is a component of a P-Channel MOS transistor; and a third P-type well 4 which is formed so as to have such a shape as to isolate the N-type well 3 from the N-type epitaxial layer 115 and which has a higher impurity concentration than that of the first P-type well 1.Type: GrantFiled: June 6, 2007Date of Patent: July 13, 2010Assignee: Panasonic CorporationInventors: Emi Ohtsuka, Mikiya Uchida, Ryohei Miyagawa
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Patent number: 7745859Abstract: A solid-state image sensing apparatus has a signal storage portion of a second conductivity type provided within a substrate, a surface shield layer of the first conductivity type provided in a surface portion of the substrate which is located above the signal storage portion, a gate electrode provided over the substrate in adjacent relation to at least one end of the signal storage portion, and a drain region of the second conductivity type provided in a surface portion of the substrate which is on the side opposite to the surface shield layer when viewed from the gate electrode. A read control layer of the first conductivity type is further provided in a surface portion of the substrate which is located under the gate electrode in adjacent relation to one end of the surface shield layer.Type: GrantFiled: January 9, 2007Date of Patent: June 29, 2010Assignee: Panasonic CorporationInventors: Tatsuya Hirata, Shouzi Tanaka, Ryohei Miyagawa, Kazunari Koga
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Patent number: 7696546Abstract: A silicide layer (first silicide layer, second silicide layer) is laminated on top laminate surfaces of gates of a transmission transistor and a reset transistor, respectively. Each of the first silicide layer and the second silicide layer respectively formed on each of the gates extends in a direction along the main surface of the semiconductor substrate among at least a portion of a plurality of image pixels, connecting gates with one another among the respective image pixels. On the other hand, a signal outputter is not in contact with any silicide layers, has the top laminate surface that is covered with an insulating layer, and is connected with other transistors via a metal wiring layer.Type: GrantFiled: January 17, 2008Date of Patent: April 13, 2010Assignee: Panasonic CorporationInventors: Tatsuya Hirata, Shouzi Tanaka, Ryohei Miyagawa
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Patent number: 7626622Abstract: A solid state image pickup device 110 is provided with: a plurality of pixel units 10 that are arranged two-dimensionally and include a photoelectric conversion unit (photodiode PD) that converts light into a charge and an amplification unit (amplifier Q13) that converts the charge into a voltage and outputs it; a plurality of noise signal removal units (noise cancellation units 40) that are provided one for each column and remove noises contained in the voltage outputted from the amplifier Q31 of the pixel unit 10 belonging to the column; and a plurality of column amplification units (column amplifiers 70) that amplify the voltage outputted from the amplifier Q13 of the pixel unit 10 and output the amplified voltage to the noise cancellation unit 40, and enables increase in sensitivity and reduction in noise with low power consumption.Type: GrantFiled: January 11, 2005Date of Patent: December 1, 2009Assignee: Panasonic CorporationInventors: Shigetaka Kasuga, Takumi Yamaguchi, Takahiko Murata, Yoshiyuki Matsunaga, Ryohei Miyagawa, Atsushi Ueta