Patents by Inventor Ryohei Miyagawa

Ryohei Miyagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070109432
    Abstract: A solid state imaging device includes an imaging area where a plurality of first pixels and a plurality of second pixels are respectively arranged in the form of a matrix, each of the first pixels and the second pixels having a photoelectric conversion portion and outputting a signal in accordance with brightness of incident light when selected; a plurality of first memories that respectively store signals of selected first pixels out of the plurality of first pixels; and a plurality of second memories that are respectively connected in parallel to the first memories and respectively store signals of selected second pixels out of the plurality of second pixels. The signals stored in the first memories and in the second memories are successively read to a horizontal signal line.
    Type: Application
    Filed: September 28, 2006
    Publication date: May 17, 2007
    Inventors: Takumi Yamaguchi, Takahiko Murata, Shigetaka Kasuga, Takayoshi Yamada, Yoshiyuki Matsunaga, Ryohei Miyagawa
  • Publication number: 20070111359
    Abstract: Realized are a solid-state image pickup device whose element patterns are miniaturized and a method for manufacturing the solid-state image pickup device, in which furnace-annealing is employed without performing a process of nitriding a gate oxide film and a rapid thermal treatment in main heat treatment processes. The method for manufacturing the solid-state image pickup device according to the present invention comprises the steps of forming respective gate insulating films of an N-channel transistor and a P-channel transistor by thermally oxidizing a semiconductor substrate; forming a gate electrode of the P-channel transistor and forming a gate electrode of the N-channel transistor so as to have a minimum gate length equal to or less than 0.3 ?m; implanting impurity into the semiconductor substrate utilizing the gate electrodes as a mask; and furnace-annealing the semiconductor substrate having the impurity implanted thereinto.
    Type: Application
    Filed: November 1, 2006
    Publication date: May 17, 2007
    Inventors: Mikiya Uchida, Ryohei Miyagawa
  • Publication number: 20060261386
    Abstract: An inversion layer is formed in a part as a boundary between (a) a defect control layer formed along a trench surface for isolating pixel calls and (a) a photo diode. The defect control layer is a P-type, and the photo diode and the inversion layer are N-type. Here, an impurity concentration in the inversion layer is at least twice as high as an impurity concentration in the photo diode.
    Type: Application
    Filed: May 17, 2006
    Publication date: November 23, 2006
    Inventors: Shouzi Tanaka, Ryohei Miyagawa
  • Publication number: 20060232693
    Abstract: To provide an imaging device having a multi-pixel cell MOS image sensor in which, even when a charge overflows to a detection part as a result that strong light falls on one photodiode and causes the photodiode to saturate, the overflowing charge can be prevented from leaking to another unsaturated photodiode. The imaging device includes a plurality of unit cells each of which includes N photodetectors, one detection part, N read transistors, one reset transistor, and one amplification transistor. Each read transistor switches ON and OFF between a corresponding photodetector and the detection part, thereby causing luminance information in the photodetector to be moved to the detection part. The reset transistor switches ON and OFF between a power supply terminal and the detection part. The amplification transistor amplifies the moved luminance information. Each of the N read transistors is an enhancement transistor, and the reset transistor is a depression transistor.
    Type: Application
    Filed: March 24, 2006
    Publication date: October 19, 2006
    Inventor: Ryohei Miyagawa
  • Publication number: 20060157756
    Abstract: An object of the present invention is to provide a solid-state imaging device which can increase the amount of signal charge accumulation in a photodiode, and a manufacturing method thereof.
    Type: Application
    Filed: November 2, 2005
    Publication date: July 20, 2006
    Inventors: Syouji Tanaka, Ryohei Miyagawa, Kazunari Koga, Tatsuya Hirata, Hiroki Nagasaki
  • Patent number: 7015522
    Abstract: A solid-state image sensor of the present invention includes a semiconductor substrate 1 having a plurality of pixels, and each of the pixels comprises an impurity layer a photoelectric converting layer, a read out region, and a gate electrode. The impurity layer includes an adjoining portion adjacent to a portion of the substrate directly beneath the gate electrode The adjoining portion includes sub-portions aligned along a width direction of a gate that is orthogonal to a transfer direction of a signal charge and a thickness direction of the substrate. An impurity density in the sub-portion 2a including a center of the adjoining portion is lower than that in the sub-portions.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: March 21, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ryohei Miyagawa, Shoji Tanaka
  • Publication number: 20050230720
    Abstract: A solid-state image sensor of the present invention includes a semiconductor substrate 1 having a plurality of pixels, and each of the pixels comprises an impurity layer 2, a photoelectric converting layer 4, a read out region 5, and a gate electrode 7. The impurity layer 2 includes an adjoining portion adjacent to a portion of the substrate 1 directly beneath the gate electrode 7. The adjoining portion includes sub-portions 2a, 2b, and 2c aligned along a width direction of a gate that is orthogonal to a transfer direction of a signal charge and a thickness direction of the substrate. An impurity density in the sub-portion 2a including a center of the adjoining portion is lower than that in the sub-portions 2b and 2c.
    Type: Application
    Filed: April 6, 2005
    Publication date: October 20, 2005
    Inventors: Ryohei Miyagawa, Shoji Tanaka
  • Patent number: 6943389
    Abstract: A solid-state imaging device comprises an image pickup unit having unit cells including opto-electrical converter elements, said unit cells being disposed in a two-dimensional array, a selection line made of polysilicon for selectively determining the unit cells in the same row within the image pickup unit, a read-out line made of polysilicon for reading out an electric charge accumulated in the opto-electrical converter elements of the unit cells in the same row within the image pickup unit, a signal line transmitting pixel signals produced from the unit cells in the same row within the image pickup unit, a reset line made of polysilicon for discharging the unit cells in the same row within the image pickup unit down to a desired voltage level, a driver circuit located on one side of the image pickup unit for supplying drive signals to the read-out line, the selection line, and the reset line, respectively, and a read-out auxiliary wiring disposed along at least the read-out line and electrically connected t
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: September 13, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Yamaguchi, Ryohei Miyagawa, Yoshitaka Egawa
  • Publication number: 20050161584
    Abstract: A solid-state imaging device includes pixels 2 arranged two-dimensionally on a semiconductor substrate 1. In a predetermined area in each pixel is formed a light-sensitive area 3 for receiving incident light 11, and each pixel includes a photoelectric conversion portion 4 for converting the incident light into a signal charge. In at least some of the pixels, the center of the light-sensitive area is offset from the center of the pixel when seen from directly above a principal surface of the semiconductor substrate. Each pixel further includes a light-path change member 12a and 12b for deflecting incident light traveling toward the center of the pixel so as to be directed toward the center of the light-sensitive area. Thus, a solid-state imaging device simultaneously realizing the miniaturization of pixels and a high image quality is provided.
    Type: Application
    Filed: August 12, 2004
    Publication date: July 28, 2005
    Inventors: Syouji Tanaka, Ryohei Miyagawa, Toshiya Fujii, Yasuhiro Tanaka, Michihiro Yamagata, Hiroaki Okayama
  • Publication number: 20040113180
    Abstract: A solid-state imaging device, comprises an image pickup unit having unit cells including opto-electrical converter elements, said unit cells being disposed in two-dimensional array, a selection line made of polysilicon for selectively determining the unit cells in the same row within the image pickup unit, a read-out line made of polysilicon for reading out electric charge accumulated in the opto-electrical converter elements of the unit cells in the same row within the image pickup unit, a signal line transmitting pixel signals produced from the unit cells in the same row within the image pickup unit, a reset line made of polysilicon for discharging the unit cells in the same row within the image pickup unit down to the desired voltage level, a driver circuit located on one side of the image pickup unit for supplying drive signals to the read-out line, the selection line, and the reset line, respectively, and a read-out auxiliary wiring disposed along at least the read-out line and electrically connected to
    Type: Application
    Filed: September 25, 2003
    Publication date: June 17, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuya Yamaguchi, Ryohei Miyagawa, Yoshitaka Egawa
  • Patent number: 6674470
    Abstract: A solid state imaging device comprises a plurality of unit cells formed in a surface region of a semiconductor substrate. Each of the unit cells comprises a photoelectric converter, an MOS-type read-out transistor for reading a signal from the photoelectric converter, an MOS-type amplifying transistor having a gate connected to a drain of the read-out transistor and for amplifying the signal read by the read-out transistor, a reset transistor having a source connected to the drain of the read-out transistor and for resetting a potential of a gate of the amplifying transistor, and an addressing element connected in series to the amplifying transistor and for selecting the unit cell. The read-out transistor is formed in a first device region in the semiconductor substrate. The reset transistor is formed in a second device region in the semiconductor substrate.
    Type: Grant
    Filed: September 19, 1997
    Date of Patent: January 6, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nagataka Tanaka, Eiji Oba, Keiji Mabuchi, Michio Sasaki, Ryohei Miyagawa, Hirofumi Yamashita, Yoshinori Iida, Hisanori Ihara, Tetsuya Yamaguchi
  • Patent number: 6617625
    Abstract: A device region surrounded by a device isolation region has a rectangular shape with a width in a direction in which a gate electrode of a transfer gate extends. A signal accumulation region of a photodiode is disposed on the entirety of that portion of the device region, which is located on a source side of the gate electrode of the transfer gate. A detection section having a width in the direction in which the gate electrode extends is disposed on that portion of the device region, which is located on a drain side of the gate electrode of the transfer gate. The size of the detection section is set to be as small as possible. Two edge portions of the detection section, which are located in the direction of extension of the gate electrode, are spaced apart from the device isolation region.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: September 9, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryohei Miyagawa
  • Patent number: 6528342
    Abstract: This invention prevents an end portion of the LOCOS region having a large number of defects of an MOS sensor from depletion and thereby reduces the leak current that occurs in the defects in the end portion of the LOCOS region. An n-type layer region is formed in a surface area of a p-type substrate for constituting a photodiode with the p-type layer. A LOCOS region is formed on a p+-type layer in a surface area of the silicon substrate as device separation region by oxidizing part of the silicon substrate. The n-type layer region and the LOCOS region are separated from each other by a predetermined distance. A contact region is formed and separated from the n-type layer region by a distance equal to the size of the gate electrode of the read-out transistor of the MOS sensor. A wiring layer is connected to the contact region. Then, a planarizing layer is formed to cover the n-type layer region, the LOCOS region, the gate electrode and the wiring layer.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: March 4, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryohei Miyagawa, Hirofumi Yamashita, Michio Sasaki, Eiji Oba, Nagataka Tanaka, Keiji Mabuchi
  • Patent number: 6507365
    Abstract: A solid-state imaging device with a variable (continuous) electronic shutter function comprises an imaging area where unit cells with photodiodes acting as pixels are arranged two-dimensionally, read lines for driving the read transistors in each pixel row, vertical selection lines for driving the vertical selection transistors in each pixel row, a vertical driving circuit for selectively driving vertical selection lines, vertical signal lines for outputting the signal from each unit cell in the pixel rows driven sequentially, and a row selection circuit for controlling the vertical driving circuit in such a manner that the vertical driving circuit drives the read transistors in each pixel row with the desired signal storage timing and signal read timing twice in that order and thereby drives the vertical selection transistors in the pixel row in synchronization with the signal read timing.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: January 14, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuo Nakamura, Yoshitaka Egawa, Shinji Ohsawa, Yukio Endo, Yoshiyuki Matsunaga, Yoriko Tanaka, Fumio Izawa, Hiroki Miura, Ryohei Miyagawa, Ikuko Inoue, Tsuyoshi Arakawa, Yoshiyuki Tomizawa, Makoto Hoshino
  • Publication number: 20010054713
    Abstract: A device region surrounded by a device isolation region has a rectangular shape with a width in a direction in which a gate electrode of a transfer gate extends. A signal accumulation region of a photodiode is disposed on the entirety of that portion of the device region, which is located on a source side of the gate electrode of the transfer gate. A detection section having a width in the direction in which the gate electrode extends is disposed on that portion of the device region, which is located on a drain side of the gate electrode of the transfer gate. The size of the detection section is set to be as small as possible. Two edge portions of the detection section, which are located in the direction of extension of the gate electrode, are spaced apart from the device isolation region.
    Type: Application
    Filed: June 25, 2001
    Publication date: December 27, 2001
    Inventor: Ryohei Miyagawa
  • Publication number: 20010032983
    Abstract: This invention prevents an end portion of the LOCOS region having a large number of defects of an MOS sensor from depletion and thereby reduces the leak current that occurs in the defects in the end portion of the LOCOS region. An n-type layer region is formed in a surface area of a p-type substrate for constituting a photodiode with the p-type layer. A LOCOS region is formed on a p+-type layer in a surface area of the silicon substrate as device separation region by oxidizing part of the silicon substrate. The n-type layer region and the LOCOS region are separated from each other by a predetermined distance. A contact region is formed and separated from the n-type layer region by a distance equal to the size of the gate electrode of the read-out transistor of the MOS sensor. A wiring layer is connected to the contact region. Then, a planarizing layer is formed to cover the n-type layer region, the LOCOS region, the gate electrode and the wiring layer.
    Type: Application
    Filed: June 21, 2001
    Publication date: October 25, 2001
    Inventors: Ryohei Miyagawa, Hirofumi Yamashita, Michio Sasaki, Eiji Oba, Nagataka Tanaka, Keiji Mabuchi
  • Patent number: 6281533
    Abstract: This invention prevents an end portion of the LOCOS region having a large number of defects of an MOS sensor from depletion and thereby reduces the leak current that occurs in the defects in the end portion of the LOCOS region. An n-type layer region is formed in a surface area of a p-type substrate for constituting a photodiode with the p-type layer. A LOCOS region is formed on a p+-type layer in a surface area of the silicon substrate as device separation region by oxidizing part of the silicon substrate. The n-type layer region and the LOCOS region are separated from each other by a predetermined distance. A contact region is formed and separated from the n-type layer region by a distance equal to the size of the gate electrode of the read-out transistor of the MOS sensor. A wiring layer is connected to the contact region. Then, a planarizing layer is formed to cover the n-type layer region, the LOCOS region, the gate electrode and the wiring layer.
    Type: Grant
    Filed: September 18, 1997
    Date of Patent: August 28, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryohei Miyagawa, Hirofumi Yamashita, Michio Sasaki, Eiji Oba, Nagataka Tanaka, Keiji Mabuchi
  • Patent number: 5506429
    Abstract: A CCD imager has an array of rows and columns of picture elements on a semiconductor substrate. A vertical charge transfer gate section extends in a first direction on the substrate to be associated with the columns. The transfer gate section includes CCD channels in the substrate, and insulated transfer gate electrodes overlying these CCD channels. A plurality of buffer electrodes are formed at a first level over the substrate surface to overlie the transfer gate electrodes. A plurality of shunt wires are formed at a second level over the substrate surface to overlie the buffer electrodes. The charge transfer gate electrodes and the buffer electrodes are connected with each other by first contact holes. The buffer electrodes and the shunt wires are coupled together by second contact holes.
    Type: Grant
    Filed: March 11, 1994
    Date of Patent: April 9, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nagataka Tanaka, Nobuo Nakamura, Yoshiyuki Matsunaga, Shinji Ohsawa, Michio Sasaki, Hirofumi Yamashita, Ryohei Miyagawa
  • Patent number: 5504526
    Abstract: A solid-state imaging device includes a substrate, and an array of charge-packet storage cells or picture elements (or "pixels") arranged on the substrate, each including a storage diode that stores therein a signal charge packet indicative of an incident light. A charge transfer section is coupled with the array of picture elements. The transfer section includes a charge-coupled device (CCD) register layer that is spaced apart from the storage diode to define a channel region therebetween, and a first insulated electrode overlying the register layer and the channel region. A reset section is coupled to the storage diode, for potentially resetting the storage diode by additionally injecting an extra charge packet into the storage diode and by causing the charge to drained from the storage diode.
    Type: Grant
    Filed: November 23, 1993
    Date of Patent: April 2, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryohei Miyagawa, Shinji Ohsawa, Hirofumi Yamashita, Michio Sasaki, Yoshiyuki Matsunaga
  • Patent number: 5463232
    Abstract: A solid-state imaging device includes an array of photosensitive cells, each of which includes a photoelectric conversion section, which is arranged on the surface of a substrate and has a light-receiving opening. The photoelectric conversion section generates a packet of electrical carriers in response to the amount of incident light thereinto through the opening. A charge transfer section is arranged adjacent to the photoelectric conversion section on the substrate surface. This transfer section defines thereunder a transfer channel region that extends linearly in a predetermined direction in the substrate surface, and causes the carriers thus obtained to move sequentially. A light-shield section is arranged to cover the photoelectric conversion section except the opening, for preventing an incident light coming through the opening from being introduced into the transfer channel region as a leak component, by cutting off an internal reflection path of the leak component thereto.
    Type: Grant
    Filed: April 8, 1993
    Date of Patent: October 31, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirofumi Yamashita, Ikuko Inoue, Michio Sasaki, Ryohei Miyagawa