Patents by Inventor Ryohei Satoh
Ryohei Satoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20020053876Abstract: A gas-discharge display panel is manufactured by sealing up a front substrate and a rear substrate by a sealing member. A relationship of Tg≧Tf exists between a glass transition point Tg of a dielectric substance formed on the front substrate and a temperature Tf at which the front substrate and the rear substrate are sealed up.Type: ApplicationFiled: August 6, 1998Publication date: May 9, 2002Inventors: MICHIFUMI KAWAI, RYOHEI SATOH, SHOICHI IWANAGA, SHIGEAKI SUZUKI, KAZUO SUZUKI, SHIGEHISA MOTOWAKI, YOSHIHIRO KATO, YUTAKA NAITO
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Patent number: 6346772Abstract: A gas discharge display device comprising a front side substrate having a plurality of first electrodes and a back side substrate having a plurality of second electrodes, wherein at least said first electrodes or second electrodes are formed by wet etching using a resist made of an inorganic material, is excellent in the ability to suppress the breakage of wiring in electrodes.Type: GrantFiled: July 13, 2001Date of Patent: February 12, 2002Assignee: Hitachi, Ltd.Inventors: Masashi Nishiki, Ryohei Satoh, Yuzo Taniguchi, Shigeaki Suzuki, Michifumi Kawai, Masahito Ijuin, Akira Yabushita, Makoto Fukushima, Tomohiko Murase
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Publication number: 20020014841Abstract: A gas discharge display device comprising a front side substrate having a plurality of first electrodes and a back side substrate having a plurality of second electrodes, wherein at least said first electrodes or second electrodes are formed by wet etching using a resist made of an inorganic material, is excellent in the ability to suppress the breakage of wiring in electrodes.Type: ApplicationFiled: July 13, 2001Publication date: February 7, 2002Inventors: Masashi Nishiki, Ryohei Satoh, Yuzo Taniguchi, Shigeaki Suzuki, Michifumi Kawai, Masahito Ijuin, Akira Yabushita, Makoto Fukushima, Tomohiko Murase
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Patent number: 6343967Abstract: A method of making a gas discharge display panel including the steps of providing a first substrate having a plurality of first electrodes and a plurality of second electrodes, laser processing said first electrodes into a rectangular form, forming the second electrodes on the first electrodes and providing a second substrate having a plurality of third electrodes and being opposed to the first substrate.Type: GrantFiled: May 10, 2001Date of Patent: February 5, 2002Assignee: Hitachi, Ltd.Inventors: Masashi Nishiki, Ryohei Satoh, Yuzo Taniguchi, Shigeaki Suzuki, Michifumi Kawai, Masahito Ijuin, Akira Yabushita, Tomohiro Murase
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Patent number: 6333599Abstract: A plasma display system has a plasma display panel including a pair of base plates for forming a plurality of discharge cells therebetween, and a plurality of pairs of electrodes for sustaining discharge to form plasma through a dielectric substance thereon in the discharge cells. The pairs of electrodes for sustaining discharge are disposed on a same one of the pair of base plates. The plasma display panel is configured such that a discharge current integrated over 40% of a discharge time Td from a start of the discharge time Td is smaller than a discharge current integrated over a remainder of the discharge time Td in one discharge, wherein the discharge time Td is defined as a time interval over which a discharge current does not drop to less than 5% of its maximum value in one discharge.Type: GrantFiled: January 19, 1999Date of Patent: December 25, 2001Assignee: Hitachi, Ltd.Inventors: Yoshimi Kawanami, Keizo Suzuki, Kenichi Yamamoto, Shirun Ho, Masaji Ishigaki, Ryohei Satoh, Masayuki Shibata, Tomohiko Murase, Michifumi Kawai
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Patent number: 6261144Abstract: A gas discharge display device comprising a front side substrate having a plurality of first electrodes and a back side substrate having a plurality of second electrodes, wherein at least said first electrodes or second electrodes are formed by wet etching using a resist made of an inorganic material, is excellent in the ability to suppress the breakage of wiring in electrodes.Type: GrantFiled: October 1, 1998Date of Patent: July 17, 2001Assignee: Hitachi, LTDInventors: Masashi Nishiki, Ryohei Satoh, Yuzo Taniguchi, Shigeaki Suzuki, Michifumi Kawai, Masahito Ijuin, Akira Yabushita, Makoto Fukushima, Tomohiko Murase
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Patent number: 6227436Abstract: In soldering together two members such as electronic circuit devices, after an oxide or contaminated layer has been removed from the surface of a solder material or bonding pad, for example, the members are aligned in an oxidizing atmosphere. Then the solder material is heated in a nonoxidizing atmosphere to melt the solder and bond the members. Cleaning of the solder material or bonding pad is performed by sputter-cleaning, laser cleaning, mechanical polishing, or cutting.Type: GrantFiled: September 25, 1998Date of Patent: May 8, 2001Assignee: Hitachi, Ltd.Inventors: Toru Nishikawa, Ryohei Satoh, Masahide Harada, Tetsuya Hayashida, Mitugu Shirai
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Patent number: 6199404Abstract: A manufacturing method for a gas discharge type display panel makes it possible to manufacture an environmentally friendly substrate with high accuracy and yet at low cost. According to the manufacturing methods electrodes are formed on a back substrate by photolithography or printing, then a glass paste is printed to a height of approximately 10 &mgr;m-500 &mgr;m by printing. A barrier rib blanks are produced by rolling under pressure the glass paste by using a roller provided with grooves. The roller is heated in advance. The barrier rib blanks are sintered into the barrier ribs.Type: GrantFiled: October 21, 1997Date of Patent: March 13, 2001Assignee: Hitachi, Ltd.Inventors: Michifumi Kawai, Ryohei Satoh, Masahito Ijuin, Tomohiko Murase, Takao Terabayashi, Nobuyuki Ushifusa, Yoshihiro Kato, Shigeaki Suzuki, Seiichi Tsuchida, Yutaka Naito, Seiichi Yasumoto, Osami Kaneto
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Patent number: 6137185Abstract: An electrode structure as well as the fabrication method thereof is disclosed which may enable successful pad layout conversion of interconnection electrode pads on the periphery of an associated IC chip to a grid array of rows and columns of terminal solder pads arranged occupying the entire area of the opposite surface of the chip while permitting use of a minimized length of wire leads for interconnection therebetween.Type: GrantFiled: March 9, 1999Date of Patent: October 24, 2000Assignee: Hitachi, Ltd.Inventors: Masakazu Ishino, Ryohei Satoh, Mamoru Mita
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Patent number: 5973406Abstract: An electronic device is solder bonded properly without using fluxes nor precise positioning with respect to a substrate. A bond pad with a size about twice the size of terminal pad of the electronic device is formed in a region on the substrate where the electronic device is to be mounted. After placing the electronic device of the substrate surface, the whole unit is heated in a nitrogen atmosphere to melt a bump formed on the terminal pad of the electronic device. The molten solder wets and spreads over the bond pads formed on the substrate, thereby establishing reflow soldering between the bond pads and the terminal pads. The position of the electronic device with respect to the substrate is spontaneously corrected due to a self-alignment function induced by wetting and spreading of the molten solder over the bond pad of the substrate.Type: GrantFiled: August 25, 1997Date of Patent: October 26, 1999Assignee: Hitachi, Ltd.Inventors: Masahide Harada, Toru Nishikawa, Ryohei Satoh, Osamu Yamada, Takayuki Uda, Mitsugu Shirai
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Patent number: 5939789Abstract: A multilayer substrate which is fabricated by laminating a plurality of substrates, each comprising an insulation film, a plurality of via holes which pass through the upper surface to the lower surface of the insulation film, a wiring which is provided on the upper surface of the insulation film and the upper surface of the via holes and electrically connected with the via holes, a bonding member which is provided on the lower surfaces of the via holes and electrically connected with the via holes, and a bonding layer which is provided on the upper surface of the insulation film where the wiring is formed and the method of fabrication thereof whereby large costs reduction and high density effect can be obtained.Type: GrantFiled: July 16, 1997Date of Patent: August 17, 1999Assignee: Hitachi, Ltd.Inventors: Michifumi Kawai, Ryohei Satoh, Osamu Yamada, Eiji Matsuda, Masakazu Ishino, Takashi Inoue, Hideo Sotokawa, Masayuki Kyoui
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Patent number: 5923539Abstract: A multilayer circuit substrate with a circuit repairing function which has a circuit substrate having a circuit pattern and repair pattern on the inner layer via an inter-substrate insulation film and having circuit repairing areas for cutting and bonding the circuit on these patterns, a terminal bonding pad for bonding electronic circuit parts mounted on this substrate, and a conductive via hole for bonding said circuit pattern to the terminal bonding pad, wherein at least the circuit repairing area of the repair pattern and at least the circuit repairing area of said circuit pattern which are set on said inner layer are brought close to each other and positioned on the same plane.Type: GrantFiled: October 25, 1995Date of Patent: July 13, 1999Assignee: Hitachi, Ltd.Inventors: Kiyoshi Matsui, Ryohei Satoh, Michifumi Kawai, Masashi Ohkubo, Yutaka Watanabe, Masakazu Yamamoto, Tsutomu Imai, Shinji Abe, Hiroyuki Hidaka
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Patent number: 5886409Abstract: An electrode structure as well as the fabrication method thereof is disclosed which may enable successful pad layout conversion of interconnection electrode pads on the periphery of an associated IC chip to a grid array of rows and columns of terminal solder pads arranged occupying the entire area of the opposite surface of the chip while permitting use of a minimized length of wire leads for interconnection therebetween.Type: GrantFiled: January 10, 1997Date of Patent: March 23, 1999Assignee: Hitachi, Ltd.Inventors: Masakazu Ishino, Ryohei Satoh, Mamoru Mita
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Patent number: 5878943Abstract: In soldering together two members such as electronic circuit devices, after an oxide or contaminated layer has been removed from the surface of a solder material or bonding pad, for example, the members are aligned in an oxidizing atmosphere. Then the solder material is heated in a nonoxidizing atmosphere to melt the solder and bond the members. Cleaning of the solder material or bonding pad is performed by sputter-cleaning, laser cleaning, mechanical polishing, or cutting.Type: GrantFiled: November 19, 1996Date of Patent: March 9, 1999Assignee: Hitachi, Ltd.Inventors: Toru Nishikawa, Ryohei Satoh, Masahide Harada, Tetsuya Hayashida, Mitugu Shirai
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Patent number: 5865365Abstract: A method of soldering used in fabricating an electronic circuit device employs an organic material supplied to at least one of the connecting members to be bonded. The connecting members are positioned in an oxidizing atmosphere, and heated in a nonoxidizing atmosphere to remove oxide and/or contamination layers present on the surface of presoldered portions or metallized bonding portions. By this method, fluxless soldering is performed, positional shifts are reduced, and high reliability of the soldering connections with reduction in residues after reflow are obtained.Type: GrantFiled: December 6, 1996Date of Patent: February 2, 1999Assignee: Hitachi, Ltd.Inventors: Toru Nishikawa, Ryohei Satoh, Masahide Hara, Tetsuya Hayashida, Mitugu Shirai, Osamu Yamada, Hiroko Takehara, Yasuhiro Iwata, Mitsunori Tamura, Masahito Ijuin
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Patent number: 5832595Abstract: A method of modifying an electronic circuit board by performing disconnection or connection of conductive lines at a specified or an arbitrary position of the conductive lines of the electronic circuit board thereby changing an electric circuit and of completely modifying an open pattern defect of the conductive lines or an insulator layer, and its device, wherein a first energy beam is irradiated to portions of repair terminals 9 and 9' which are intended to connect or disconnect, of conductive lines 5 and 5' in the electronic circuit board thereby removing a protection layer, making windows and exposing the terminals 9 and 9' for connection; a second energy beam is irradiated thereby disconnecting the repair terminals 9 and 9', or a metal piece for connecting is supplied to between the repair terminals 9 and 9' and applying an energy thereto thereby electrically connecting them; and the disconnected or connected windowed portion is locally coated with the insulator layer thereby modifying the conductive linType: GrantFiled: June 14, 1994Date of Patent: November 10, 1998Assignee: Hitachi, Ltd.Inventors: Shigenobu Maruyama, Mikio Hongo, Haruhisa Sakamoto, Tateoki Miyauchi, Ryohei Satoh, Kiyoshi Matsui, Shinichi Kazui, Kaoru Katayama, Hiroshi Fukuda
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Patent number: 5816473Abstract: An apparatus comprises a sputter cleaning device, an alignment device operable in atmospheric condition and a heating and soldering device in the form of a belt furnace operable in non-oxidizing or reducing environment. Instead of the sputter cleaning device, a mechanical polishing or cutting device can be used to clean a surface of solder or a member to be bonded or a solder ball plated with gold may be used. An alignment between two members to be bonded is provided by an alignment mark means which comprises a protrusion on a surface of one member and a complimentary recess formed at a center portion of a protrusion means formed on a corresponding surface of the other member.Type: GrantFiled: December 22, 1995Date of Patent: October 6, 1998Assignee: Hitachi, Ltd.Inventors: Toru Nishikawa, Ryohei Satoh, Masahide Harada, Tetsuya Hayashida, Mitugu Shirai
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Patent number: 5731066Abstract: In an electronic circuit device having an input/output pin junction electrode, in order to remarkably improve the junction characteristics such as wettability and junction strength and to drastically simplify the production process, in forming an electronic circuit board in which glass ceramics is used for board material and a wiring conductor and junction electrode wherein the Cu is sized to extend beyond the pin hole so that solder only contacts it and not the ceramic circuit board. The wiring and junction electrode is formed in a same process while forming a cover coat on the electrode using board material, and Au or Au--Ni laminated film is formed on this electrode as occasion demands, and then an electronic component is connected thereto using a solder such a Au--Sn or Au--Ge.Type: GrantFiled: October 23, 1995Date of Patent: March 24, 1998Assignee: Hitachi, Ltd.Inventors: Akihiro Ando, Osamu Yamada, Ryohei Satoh, Takashi Inoue, Masahide Okamoto, Fumiyuki Kobayashi, Toshihiko Ohta, Minoru Tanaka
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Patent number: 5476726Abstract: A solder bonding metal layer which is formed on a circuit board comprises a metal layer having a mixture of first metal which is easily wetted with metals constituting the solder and which easily forms alloy or intermetallic compounds and of second metal which is not wetted easily with the above solder and not melted. In this case, a concentration gradient that the concentration of the first metal is high on the bonding surface may be formed in the metal layer. A circuit board having a solder bonding metal layer which keeps good bonding even after many times of repairs and improves the reliability is realized.Type: GrantFiled: January 19, 1993Date of Patent: December 19, 1995Assignee: Hitachi, Ltd.Inventors: Masahide Harada, Akihiro Ando, Ryohei Satoh, Akira Yabushita, Naoya Kanda, Kazuhiko Horikoshi
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Patent number: 5341980Abstract: In a method of soldering for use in fabricating electronic circuit device, after an oxide layer and/or contaminated layer on a surface of a soldering material and members to be soldered thereby is removed by sputter-cleaning with atom or ion, the members are aligned in an oxidizing atmosphere within a predetermined time period and, then, the soldering material is heated in non-oxidizing atmosphere to performe soldering. An apparatus for performing the above method comprises a sputter cleaning device, an alignment device operable in atmospheric condition and a heating and soldering device in the form of a belt furnace operable in non-oxidizing or reducing environment. Instead of the sputter cleaning device, a mechanical polishing or cutting device can be used to cleaning a surface of solder or a member to be bonded or a solder ball plated with gold may be used.Type: GrantFiled: May 29, 1992Date of Patent: August 30, 1994Assignee: Hitachi, Ltd.Inventors: Toru Nishikawa, Ryohei Satoh, Masahide Harada, Tetsuya Hayashida, Mitugu Shirai