Patents by Inventor Ryohei Satoh

Ryohei Satoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5291419
    Abstract: A method for evaluating the life of a connection between members including the steps of extracting parameters defining the shearing strain of a predetermined model representing the connection thereby to calculate the values of plural shearing strains of the connection, calculating the equivalent strain amplitude corresponding to thermal fatigue stress for each of the values of the plural shearing strains defining the relationship between the shearing strain and the equivalent strain amplitude, formulating a life evaluation criterion equation expressed using the equivalent strain amplitude, calculating, for the connection, the equivalent strain amplitude corresponding to each of the shearing strains actually measured using the equation, and substituting the equivalent strain amplitude for the life evaluation criterion equation to acquire the life of the connection.
    Type: Grant
    Filed: January 6, 1992
    Date of Patent: March 1, 1994
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Ryohei Satoh, Katsuhiro Arakawa, Kiyoshi Kanai, Tsutomu Takahashi, Takaji Takenaka, Haruhiko Imada
  • Patent number: 5276289
    Abstract: The present invention provides a multistep electronic circuit device comprising a plurality of parts and elements mechanically or electrically bonded in sequence to each other and to a substrate with a plurality of solders, which comprises as the parts and elements the substrate, input and output pins and LSI chips, and optionally packages and a cooler bonded through multistep bonding, the bondings of the parts and elements including at least one CCB bonding and at least one sealing, the solders each having a lower melting point than the heatproof temperature of the part or element to be bonded with the solder, and one of the solders having a melting point of at least 10.degree. C. lower than that of the other solder used at the bonding step immediately before. The solders used are selected from Au10-15wt%Ge alloy (melting point: 356.degree.-450.degree. C.), Pb1-5wt%Sn alloy (melting point: 314.degree.-325.degree. C.), Pb10-13wt%Sn alloy (melting point: 270.degree.-300.degree. C.
    Type: Grant
    Filed: March 25, 1991
    Date of Patent: January 4, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Ryohei Satoh, Fumiyuki Kobayashi, Yutaka Watanabe, Tositada Netsu, Mitugu Shirai, Kenji Takeda, Masahide Harada, Kiyoshi Matsui, Hideaki Sasaki
  • Patent number: 5249100
    Abstract: Disclosed is an electronic circuit device in which the solder (14) connecting lead pins (6) to the ceramic substrate (2) has a melting point of 356.degree. C. to 450.degree. C. and has a tensile strength being low in such an extent that a thermal contraction stress generated in a cooling process of the solder (14) from the melting point thereof is low and the substrate (2) does not break. The solder (14) is a Au-Ge alloy containing 10-15 wt % of Ge. Electronic circuit devices, which employ the above solder (14) in the connections, are free from damages in the ceramic wiring substrate (2) due to the bonding. Further, when the electronic circuit device undergoes a series of assembly processes after the above bonding, such solder (14) does not melt, and wettability of such solder (14) is favorable.
    Type: Grant
    Filed: May 11, 1990
    Date of Patent: September 28, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Ryohei Satoh, Kazuo Hirota, Takaji Takenaka, Hideki Watanabe, Toshinori Ameya, Toshihiko Ohta
  • Patent number: 5151773
    Abstract: An electronic circuit apparatus in which electronic circuit components are mounted to multiwiring substrate or the like for use with electronic circuits such as an LSI are sealed airtight by sealing units. The sealing unit is sealed by an upper board designated as an upper board sealing unit and a side board designated as a side board sealing unit, and the shape of the edge on cross section of the side board is convex or circular. Metallization is applied to solder joint portions between a substrate and a side board and between the side board and the upper board, and a predetermined solder joint height is provided by a support post to effect solder joining.
    Type: Grant
    Filed: March 28, 1991
    Date of Patent: September 29, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Kiyoshi Matsui, Ryohei Satoh, Toshitada Netsu, Hideaki Sasaki, Mitugu Shirai, Kenichi Hamamura
  • Patent number: 5136360
    Abstract: An electronic circuit device comprising an electronic part having a gold-plated connecting terminal arranged thereon connected through a solder to a circuit substrate on the predetermined connecting element thereof, in which the connecting terminal of the electronic part and the solder-connected portion of the circuit substrate are constituted by an alloy composition consisting of 1.0 to 8.0 wt. % of Ag, 0.1 to 6.0 wt % of Au and the balance of Sn, is provided. The device is made by using a solder for use in connecting a gold-plated connecting terminal which consists of 1.0 to 8.
    Type: Grant
    Filed: August 6, 1990
    Date of Patent: August 4, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Masahide Harada, Ryohei Satoh, Fumiyuki Kobayashi, Takaji Takenaka, Toshitada Netsu, Hideaki Sasaki, Mitugu Shirai
  • Patent number: 5023407
    Abstract: A metal layer other than gold is formed on a ceramic substrate, a gold layer is further formed on said metal layer, and then a high density beam is applied to the treated substrate member. Thereby, the metal of the underlayer diffused through the grain boundaries of gold up to the surface of the gold layer by heat treatment or the like is uniformly mixed with gold to form an alloyed layer excellent in wettability to a solder. At the same time, nonmetallic impurities such as carbon adhering onto the surface of the gold layer are melted and removed.
    Type: Grant
    Filed: August 7, 1989
    Date of Patent: June 11, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Mitugu Shirai, Kaoru Katayama, Hideaki Sasaki, Shinichi Kazui, Ryohei Satoh, Tateoki Miyauchi, Mamoru Kobayashi
  • Patent number: 4908696
    Abstract: The present invention relates to a connector structure for soldering a wiring substrate such as a ceramic wiring substrate to a connector provided on a printed board and also pertains to semiconductor device packages using the same. It is an object of the present invention to provide a connector structure which provides highly reliable electrical connection, together with semiconductor device package using the same. The object is attained by soldering a ceramic wiring substrate to a connector which involves a heater.
    Type: Grant
    Filed: September 16, 1987
    Date of Patent: March 13, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Shousaku Ishihara, Hitoshi Yokono, Tsuyoshi Fujita, Ryohei Satoh, Kiyotaka Wasai
  • Patent number: 4687939
    Abstract: An ion beam apparatus which comprises an enclosure defining a chamber of high vacuum. A crucible for producing vapor of a material, ionizing means, ion accelerating means, and a substrate to be deposited with the vaporized material to thereby form a film thereon are disposed within the chamber. An accelerating voltage is applied across the crucible and the accelerating means such that the crucible is of positive polarity while the accelerating means is of negative polarity. The material contained in the crucible is vaporized by heating. A pressure difference is maintained between the vapor pressure within the crucible and the vacuum chamber.
    Type: Grant
    Filed: November 6, 1984
    Date of Patent: August 18, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Tateoki Miyauchi, Hiroshi Yamaguchi, Mikio Hongo, Katsuro Mizukoshi, Akira Shimase, Ryohei Satoh
  • Patent number: 4673772
    Abstract: In connecting an electronic circuit part such as a semiconductor or other part to a substrate for mounting the part with solder, the solder is composed of a high-melting-point solder portion which is subjected to working such as rolling and heat treatment in order to break the cast structure thereof, and a smaller volume of low-melting-point solder portions. The high-melting-point solder portion is connected to both the electronic circuit substrate and the electronic circuit part through the low-point-melting solder portions.This method enables interconnection between objects to be connected without impairing the high ductility and toughness of the high-melting-point solder which is subjected to working and heat treatment. This soldering method ensures highly reliable manufacture of miniaturized high density circuits, such as LSI.
    Type: Grant
    Filed: October 4, 1985
    Date of Patent: June 16, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Ryohei Satoh, Muneo Oshima, Minoru Tanaka, Suguru Sakaguchi, Akira Murata, Kazuo Hirota