Abstract: A method for forming a semiconductor device is provided including processing a wafer having a target material, forming a multilevel photoresist structure having a protection layer over the target material, and forming a multilevel recess in the target material with the multilevel photoresist structure.

Abstract: A multilayer interconnect structure is formed by, providing a substrate (40) having thereon a first dielectric (50, 27) for supporting a multi-layer interconnection (39) having lower conductor MN (22, 23), upper conductor MN+1 (34, 35), dielectric interlayer (DIL) (68) and interconnecting via conductor VN+1/N (36, 36?). The lower conductor MN (22, 23) has a first upper surface (61) located in a recess below a second upper surface (56) of the first dielectric (50, 27). The DIL (68) is formed above the first (61) and second (56) surfaces. A cavity (1263) is etched through the DIL (68) from a desired location (122) of the upper conductor MN+1 (34), exposing the first surface (61). The cavity (1263) is filled with a further electrical conductor (80) to form the upper conductor MN+1 (34) and the connecting via conductor VN+1/N (36, 36?) making electrical contact with the first upper surface (61).

Abstract: An optical polarizer positioned before a light source for use in semiconductor wafer lithography including an array of aligned nanotubes. The array of aligned nanotubes cause light emitted from the light source and incident on the array of aligned nanotubes to be converted into polarized light for use in the semiconductor wafer lithography. The amount of polarization can be controlled by a voltage source coupled to the array of aligned nanotubes. Chromogenic material of a light filtering layer can vary the wavelength of the polarized light transmitted through the array of aligned nanotubes.

Abstract: A multilayer interconnect structure is formed by, providing a substrate having thereon a first dielectric for supporting a multi-layer interconnection having lower conductor MN, upper conductor MN+1, dielectric interlayer (DIL) and interconnecting via conductor VN+1/N. The lower conductor MN has a first upper surface located in a recess below a second upper surface of the first dielectric. The DIL is formed above the first and second surfaces. A cavity is etched through the DIL from a desired location of the upper conductor MN+1, exposing the first surface. The cavity is filled with a further electrical conductor to form the upper conductor MN+1 and the connecting via conductor VN+1/N making electrical contact with the first upper surface. A critical dimension between others of lower conductors MN and the via conductor VN+1/N is lengthened. Leakage current and electro-migration there-between are reduced.

Abstract: Ultrafine dimensions are accurately and efficiently formed in a target layer using a spacer lithographic technique comprising forming a first mask pattern, forming a cross-linkable layer over the first mask pattern, forming a cross-linked spacer between the first mask pattern and cross-linkable layer, removing the cross-linkable layer, cross-linked spacer from the upper surface of the first mask pattern and the first mask pattern to form a second mask pattern comprising remaining portions of the cross-linked spacer, and etching using the second mask pattern to form an ultrafine pattern in the underlying target layer.

Abstract: A multilayer interconnect structure is formed by, providing a substrate (40) having thereon a first dielectric (50, 27) for supporting a multi-layer interconnection (39) having lower conductor MN (22, 23), upper conductor MN+1 (34, 35), dielectric interlayer (DIL) (68) and interconnecting via conductor VN+1/N (36, 36?). The lower conductor MN (22, 23) has a first upper surface (61) located in a recess below a second upper surface (56) of the first dielectric (50, 27). The DIL (68) is formed above the first (61) and second (56) surfaces. A cavity (1263) is etched through the DIL (68) from a desired location (122) of the upper conductor MN+1 (34), exposing the first surface (61). The cavity (1263) is filled with a further electrical conductor (80) to form the upper conductor MN+1 (34) and the connecting via conductor VN+1/N (36, 36?) making electrical contact with the first upper surface (61).

Abstract: In one disclosed embodiment, a method for forming a high resolution resist pattern on a semiconductor wafer involves forming a layer of resist comprising, for example a polymer matrix and a catalytic species, over a material layer formed over a semiconductor wafer; exposing the layer of resist to patterned radiation; and applying a magnetic field to the semiconductor wafer during a post exposure bake process. In one embodiment, the patterned radiation is provided by an extreme ultraviolet (EUV) light source. In other embodiments, the source of patterned radiation can be an electron beam, or ion beam, for example. In one embodiment, the polymer matrix is an organic polymer matrix such as, for example, styrene, acrylate, or methacrylate. In one embodiment, the catalytic species can be, for example, an acid, a base, or an oxidizing agent.

Abstract: A semiconductor device is formed with sub-resolution features and at least one additional feature having a relatively larger critical dimension using only two masks. An embodiment includes forming a plurality of first mandrels, having a first width, and at least one second mandrel, having a second width greater than the first width, overlying a target layer using a first mask, forming sidewall spacers along the length and width of the first and second mandrels, forming a filler adjacent each sidewall spacer, the filler having the first width, removing the filler adjacent sidewall spacers along the widths of the first and second mandrels using a second mask, removing the sidewall spacers, and etching the target layer between the filler and the first and second mandrels, thereby forming at least two target features with different critical dimensions.

Abstract: Ultrafine patterns with dimensions smaller than the chemical and optical limits of lithography are formed by superimposing two photoresist patterns using a double exposure technique. Embodiments include forming a first resist pattern over a target layer to be patterned, forming a protective cover layer over the first resist pattern, forming a second resist pattern on the cover layer superimposed over the first resist pattern while the cover layer protects the first resist pattern, selectively etching the cover layer with high selectivity with respect to the first and second resist patterns leaving an ultrafine target pattern defined by the first and second resist patterns, and etching the underlying target layer using the superimposed first and second resist patterns as a mask.

Abstract: A method for forming an interconnect structure includes forming a mandrel above a base layer, forming spacers on the mandrel, forming recesses in the base layer using the spacers as an etch template, and forming a conductive material in the recesses.

Abstract: Disclosed herein are various methods of forming methods of forming a non-planar cap layer above a conductive line on a semiconductor device, and to devices incorporating such a non-planar cap layer. In one illustrative example, the method includes forming a conductive structure in a layer of insulating material, recessing an upper surface of the conductive structure relative to an upper surface of the layer of insulating material such that the recessed upper surface of the conductive structure and the upper surface of the layer of insulating material are positioned in different planes and, after recessing the upper surface of the conductive structure, forming a first cap layer on the conductive structure and the layer of insulating material.

Abstract: Methods are provided for fabricating a semiconductor device on and in a semiconductor substrate. In one embodiment, a method comprises the steps of forming etch masking features overlying the semiconductor substrate, the etch masking features having a first thickness, and forming an etch barrier layer overlying the substrate, the etch barrier layer having a second thickness less than or substantially equal to the first thickness. The method also comprises removing the etch masking features to expose the substrate, and etching the substrate using the etch barrier layer as an etch mask.

Abstract: A multilayer interconnect structure is formed by, providing a substrate (40) having thereon a first dielectric (50, 27) for supporting a multi-layer interconnection (39) having lower conductor MN (22, 23), upper conductor MN+1 (34, 35), dielectric interlayer (DIL) (68) and interconnecting via conductor VN+1/N (36, 36?). The lower conductor MN (22, 23) has a first upper surface (61) located in a recess below a second upper surface (56) of the first dielectric (50, 27). The DIL (68) is formed above the first (61) and second (56) surfaces. A cavity (1263) is etched through the DIL (68) from a desired location (122) of the upper conductor MN+1 (34), exposing the first surface (61). The cavity (1263) is filled with a further electrical conductor (80) to form the upper conductor MN+1 (34) and the connecting via conductor VN+1/N (36, 36?) making electrical contact with the first upper surface (61).

Abstract: A method for forming a semiconductor device is provided including processing a wafer having a target material; forming a first pattern over the target material; forming a protection layer over the first pattern; and forming a second pattern, over the target material and not over the protection layer, without an etching step between the forming the first pattern and the forming the second pattern.

Abstract: A method for forming an interconnect structure includes forming a mandrel above a base layer, forming spacers on the mandrel, forming recesses in the base layer using the spacers as an etch template, and forming a conductive material in the recesses.

Abstract: A semiconductor device is formed with sub-resolution features and at least one additional feature having a relatively larger critical dimension using only two masks. An embodiment includes forming a plurality of first mandrels, having a first width, and at least one second mandrel, having a second width greater than the first width, overlying a target layer using a first mask, forming sidewall spacers along the length and width of the first and second mandrels, forming a filler adjacent each sidewall spacer, the filler having the first width, removing the filler adjacent sidewall spacers along the widths of the first and second mandrels using a second mask, removing the sidewall spacers, and etching the target layer between the filler and the first and second mandrels, thereby forming at least two target features with different critical dimensions.

Abstract: Focus monitoring for a photolithographic applications is provided by illuminating a photoresist layer with a light beam transmitted through a first binary mask to define a circuit pattern on an underlying substrate and then illuminating the photoresist layer with an unbalanced off-axis light beam transmitted through a second binary mask. The second mask contains a shifting feature configuration in one portion, while another portion blocks light transmission to the chip design area of the photoresist. After development of the photoresist layer, the pattern formed by illumination of the second mask can be compared with a predefined reference feature on the photoresist layer to determine whether a shift, if any, is within acceptable focus limits.

Abstract: Methods are provided for fabricating a semiconductor device on and in a semiconductor substrate. In one embodiment, a method comprises the steps of forming etch masking features overlying the semiconductor substrate, the etch masking features having a first thickness, and forming an etch barrier layer overlying the substrate, the etch barrier layer having a second thickness less than or substantially equal to the first thickness. The method also comprises removing the etch masking features to expose the substrate, and etching the substrate using the etch barrier layer as an etch mask.

Abstract: An integrated circuit fabrication process as described herein employs a photoresist stabilization step where patterned photoresist material is exposed to radiation having a wavelength that promotes cross-linking in the shallow surfaces of the patterned photoresist features. The patterned photoresist material is highly absorptive of the stabilizing radiation, which results in the surface cross-linking and modification of the outer surfaces of the patterned photoresist material. This modified “shell” is immune to photoresist developer, photoresist solvents, intense ion implantation, and intense etchants. The shell also enables for the resist not to deform when baked at a temperature above its glass transition temperature. For example, the photoresist stabilization technique can be used in a double exposure process such that a patterned photoresist layer remains intact during a subsequent lithographic sub-process.

Abstract: Accurate ultrafine patterns are formed using a multiple exposure technique comprising implementing an OPC procedure to form an exposure reticle to compensate for distortion of an overlying resist pattern caused by an underlying resist pattern. Embodiments include forming a first resist pattern in a first resist layer over a target layer using a first exposure reticle, forming a second exposure reticle by an OPC technique to compensate for distortion of a second resist pattern caused by the underlying first resist pattern, depositing a second resist layer on the first resist pattern, forming the second resist pattern in the second resist layer using the second exposure reticle, the first and second resist patterns constituting a final resist mask, and forming a pattern in the target layer using the final resist mask.