Abstract: Methods of forming features having differing pitch spacing and critical dimensions are disclosed herein. One method includes forming an underlying layer of material above a semiconductor substrate. The method further includes forming a masking layer above the underlying layer of material. The masking layer includes features positioned above a first region of the substrate and features positioned above a second region of the substrate. The features have different pitch spacing and critical dimensions. The method further includes performing at least one etching process on the underlying layer of material through the masking layer.

Abstract: Methods of forming integrated circuits and multiple CD SADP processes are provided that include providing a patternable structure including a first hard mask layer and a first patternable layer underlying the first hard mask layer. Mandrels are provided over the first hard mask layer. Sidewall spacers are formed adjacent sidewalls of the mandrels. The mandrels are removed, with the sidewall spacers remaining and defining gaps therebetween. The first hard mask layer is etched through the gaps to form a first patterned hard mask feature and a second patterned hard mask feature. A critical dimension of the first patterned hard mask feature is selectively modified to form a biased hard mask feature. A space is defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature. The first patternable layer is etched through exposed material in the space.

Abstract: One illustrative method disclosed herein includes, among other things, forming a multi-layer patterned masking layer comprised of first and second layers of material and first and second openings that extend through both of the first and second layers of material, wherein the first opening is positioned above a first area of the substrate where the DDB isolation structure will be formed and the second opening is positioned above a second area of the substrate where the SDB isolation structure will be formed. The method also includes performing a first process operation through the first opening to form the DDB isolation structure, performing a second process operation to remove the second layer of material and to expose the first opening in the first layer of material, and performing a third process operation through the second opening to form the SDB isolation structure.

Abstract: A method of forming a semiconductor device with uniform regular shaped gate contacts and the resulting device are disclosed. Embodiments include forming first and second gate electrodes adjacent one another on a substrate; forming at least one trench silicide (TS) on the substrate between the first and second gate electrodes; forming a gate contact on the first gate electrode, the gate contact having a regular shape; forming a source/drain contact on a trench silicide between the first and second gate electrodes, wherein an upper portion of the source/drain contact overlaps an upper portion of the gate contact.

Abstract: A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and dummy fins on a substrate, the dummy fins adjacent to each other and between the active fins; forming STI regions between and next to the active and dummy fins; forming gate structures in parallel across the active and dummy fins; forming a gate cut region by cutting the gate structures between the dummy fins; forming a TS layer between the gate structures, the TS layer crossing the gate cut region; and forming a contact connecting a gate structure and the TS layer on a first side of the gate cut region and forming a contact connecting a gate structure and the TS layer on a second side of the gate cut region, the TS layer and contacts cross coupling the gate structures.

Abstract: Methods of forming features having differing pitch spacing and critical dimensions are disclosed herein. One method includes forming an underlying layer of material above a semiconductor substrate. The method further includes forming a masking layer above the underlying layer of material. The masking layer includes features positioned above a first region of the substrate and features positioned above a second region of the substrate. The features have different pitch spacing and critical dimensions. The method further includes performing at least one etching process on the underlying layer of material through the masking layer.

Abstract: A method of optical proximity correction (OPC) in extreme ultraviolet lithography (EUV) lithography includes providing a patterned layout design including first and second design polygons that correspond with the pre-pattern opening, wherein the first and second design polygons are separated by a separation distance, and correcting the patterned layout design using OPC by generating (1) a third polygon that has dimensions corresponding to a combination of the first and second design polygons and the separation distance and (2) and filled polygon within the third polygon, thereby generating an OPC-corrected patterned layout design. EUV photomasks may be manufactured from the OPC-corrected patterned layout design, and integrated circuits may be fabricated using such EUV photomasks.

Abstract: One illustrative method disclosed herein includes forming first sacrificial gate structures above a fin for two active gates and a dummy gate, removing the first sacrificial gate structure for the dummy gate so as to define a cavity that exposes the fin while leaving the first sacrificial gate structures for the two active gates intact, etching through the cavity to form a trench in the fin under the cavity, forming a second sacrificial gate structure for the dummy gate, removing the first sacrificial gate structures for the two active gates and the second sacrificial gate structure for the dummy gate so as to define a replacement gate cavity for the two active gates and the dummy gate, and forming a replacement gate structure in each of the replacement gate cavities, wherein the replacement gate structure for the dummy gate extends into the trench in the fin.

Abstract: A method of forming a semiconductor device with uniform regular shaped gate contacts and the resulting device are disclosed. Embodiments include forming first and second gate electrodes adjacent one another on a substrate; forming at least one trench silicide (TS) on the substrate between the first and second gate electrodes; forming a gate contact on the first gate electrode, the gate contact having a regular shape; forming a source/drain contact on a trench silicide between the first and second gate electrodes, wherein an upper portion of the source/drain contact overlaps an upper portion of the gate contact.

Abstract: A method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess that have an outer perimeter surface that contacts at least a portion of an interior perimeter surface of the recess and forming at least one source/drain contact structure for each of the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure. The upper surface of each of the buried fin contact structures is positioned below an upper surface of the raised isolation structure and an outer perimeter surface of each of the buried fin contact structures contacts at least a portion of an interior perimeter surface of the recess.

Abstract: A method of contact formation and resulting structure is disclosed. The method includes providing a starting semiconductor structure, the structure including a semiconductor substrate with fins coupled to the substrate, a bottom portion of the fins being surrounded by a first dielectric layer, dummy gates covering a portion of each of the fins, spacers and a cap for each dummy gate, and a lined trench between the gates extending to and exposing the first dielectric layer. The method further includes creating an epitaxy barrier of hard mask material between adjacent fins in the trench, creating N and P type epitaxial material on the fins adjacent opposite sides of the barrier, and creating sacrificial semiconductor epitaxy over the N and P type epitaxial material, such that subsequent removal thereof can be done selective to the N and P type of epitaxial material.

Abstract: One illustrative method disclosed herein includes forming first sacrificial gate structures above a fin for two active gates and a dummy gate, removing the first sacrificial gate structure for the dummy gate so as to define a cavity that exposes the fin while leaving the first sacrificial gate structures for the two active gates intact, etching through the cavity to form a trench in the fin under the cavity, forming a second sacrificial gate structure for the dummy gate, removing the first sacrificial gate structures for the two active gates and the second sacrificial gate structure for the dummy gate so as to define a replacement gate cavity for the two active gates and the dummy gate, and forming a replacement gate structure in each of the replacement gate cavities, wherein the replacement gate structure for the dummy gate extends into the trench in the fin.

Abstract: Methods for utilizing metal segments of an additional metal layer as landing pads for vias and also as local interconnects between contacts in an IC device and resulting devices are disclosed. Embodiments include forming source/drain and gate contacts connected to transistors on a substrate in an integrated circuit device, each contact having an upper surface with a first area; forming metal segments in a plane at the upper surface of the contacts, each metal segment being in contact with one or more of the contacts and having a second area greater than the first area; and forming one or more vias between one or more of the metal segments and one or more first segments of a first metal layer.

Abstract: One illustrative method disclosed herein includes, among other things, forming a first plurality of fins in the first region of the substrate, a second plurality of fins in the second region of the substrate, and a space in the substrate between two adjacent fins in the second region that corresponds to a first isolation region to be formed in the second region, forming a fin removal masking layer above the first and second regions of the substrate, wherein the fin removal masking layer has an opening positioned above at least a portion of at least one of the first plurality of fins, while masking all of the second plurality of fins in the second region and the space for the first isolation region, and performing an etching process through the first opening to remove the portions of the at least one of the first plurality of fins.

Abstract: A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and dummy fins on a substrate, the dummy fins adjacent to each other and between the active fins; forming STI regions between and next to the active and dummy fins; forming gate structures in parallel across the active and dummy fins; forming a gate cut region by cutting the gate structures between the dummy fins; forming a TS layer between the gate structures, the TS layer crossing the gate cut region; and forming a contact connecting a gate structure and the TS layer on a first side of the gate cut region and forming a contact connecting a gate structure and the TS layer on a second side of the gate cut region, the TS layer and contacts cross coupling the gate structures.

Abstract: One illustrative device disclosed herein includes, among other things, an active region defined in a semiconductor substrate, a layer of material positioned above the substrate, a plurality of laterally spaced-apart source/drain trenches formed in the layer of material above the active region, a conductive source/drain contact structure formed within each of the source/drain trenches, a gate trench formed at least partially in the layer of material between the spaced-apart source/drain trenches in the layer of material, wherein portions of the layer of material remain positioned between the source/drain trenches and the gate trench, a gate structure positioned within the gate trench, and a gate cap layer positioned above the gate structure.

Abstract: A device includes at least one fin defined in a semiconductor substrate, a raised isolation structure surrounding and laterally spaced apart from the fin, and a gate structure extending across and positioned around a first portion of the fin. A buried fin contact structure is positioned inside of the raised isolation structure and extends across, is positioned around, and conductively contacts a second portion of the fin. An upper surface of the buried fin contact structure is positioned level with or below an upper surface of the raised isolation structure. A stress-inducing material layer is positioned on and in contact with the upper surface of the buried fin contact structure, an insulating material layer is positioned above the stress-inducing material layer and the raised isolation structure, and a contact structure extends through at least the insulating and stress-inducing material layers and conductively contacts the buried fin contact structure.

Abstract: Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a patternable structure having first and second regions and including upper and lower mandrel layers. The method etches upper mandrels from the upper mandrel layer in the first and second regions. The method includes forming first upper spacer structures having a first width adjacent upper mandrels in the first region and forming second upper spacer structures having a second width not equal to the first width adjacent upper mandrels in the second region. The method etches the lower mandrel layer using the first and second upper spacer structures as an etch mask to form lower mandrels. Further, the method includes forming spacers adjacent the lower mandrels and etching a material using the spacers as an etch mask to form variably spaced features.

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming fin structures in a selected area of a semiconductor substrate. The method includes covering the fin structures and the semiconductor substrate with a mask and forming a trench in the mask to define no more than two exposed fin structures in the selected area. Further, the method includes removing the exposed fin structures to provide the selected area with a desired number of fin structures.

Abstract: One device disclosed herein includes an active region defined in a semiconductor substrate, a layer of material positioned above the semiconductor substrate, first and second laterally spaced-apart source/drain trenches defined in the layer of material above the active region, first and second conductive source/drain contact structures positioned within the first and second laterally spaced-apart source/drain trenches, respectively, a gate trench formed at least partially in the layer of material between the first and second laterally spaced-apart source/drain trenches in the layer of material, wherein portions of the layer of material remain positioned between the first and second laterally spaced-apart source/drain trenches and the gate trench, a gate structure positioned within the gate trench, and a gate cap layer positioned above the gate structure.